When trying to rematerialize a value before an instruction that has an
early-clobber redefine of the virtual register, make sure to look up the
correct value number.

Early-clobber defs are moved one slot back, so getBaseIndex is needed to
find the used value number.

Bugpoint was unable to reduce the test case for this, see PR10388.

llvm-svn: 135378

llvm-svn: 135375

llvm-svn: 135362

llvm-svn: 135354

llvm-svn: 135352

llvm-svn: 135339

This should unbreak the build-self-4-mingw32 tester. I have a very
complicated test case that I will try to clean up.

llvm-svn: 135329

llvm-svn: 135320

and just use the ones from TargetLowering directly.

llvm-svn: 135318

llvm-svn: 135311

This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.

Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.

llvm-svn: 135307

llvm-svn: 135305

llvm-svn: 135302

llvm-svn: 135278

llvm-svn: 135265

llvm-svn: 135254

llvm-svn: 135232

Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.

llvm-svn: 135219

llvm-svn: 135212

Improve DbgScope->dump() output.

llvm-svn: 135207

when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

llvm-svn: 135180

llvm-svn: 135154

[VECTOR-SELECT]
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.

llvm-svn: 135144

llvm-svn: 135143

Original commit message:

Count references to interference cache entries.

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135130

llvm-svn: 135127

Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.

llvm-svn: 135126

llvm-svn: 135124

Fixes rdar://9761830

llvm-svn: 135123

llvm-svn: 135122

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135121

llvm-svn: 135118

The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.

The correct fix here is to use reference counts on the cache entries.
Coming up.

llvm-svn: 135113

llvm-svn: 135111

llvm-svn: 135110

llvm-svn: 135096

Some pysical registers create split solutions that would spill anywhere.
They should not even be considered in future multi-way global splits.

This does not affect code generation (yet).

llvm-svn: 135080

This is in preparation of supporting multiple global split candidates in
a single live range split operation.

llvm-svn: 135074

llvm-svn: 135068

llvm-svn: 135040