llvm-svn: 93229

llvm-svn: 93228

llvm-svn: 93227

llvm-svn: 93222

condition is a xor with a phi node.  This eliminates nonsense
like this from 176.gcc in several places:

 LBB166_84:
        testl   %eax, %eax
-       setne   %al
-       xorb    %cl, %al
-       notb    %al
-       testb   $1, %al
-       je      LBB166_85
+       je      LBB166_69
+       jmp     LBB166_85

This is rdar://7391699

llvm-svn: 93221

llvm-svn: 93220

instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.

llvm-svn: 93210

on branches by renaming it and checking for a branch at the call site.

llvm-svn: 93208

llvm-svn: 93206

Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.

llvm-svn: 93204

llvm-svn: 93203

codegen has no apparent problem with the trunc version of this, because it turns
into a simple subreg idiom

llvm-svn: 93202

trunc has multiple uses.  Codegen is not able to coalesce the subreg case 
correctly and so this leads to higher register pressure and spilling (see PR5997).

This speeds up 256.bzip2 from 8.60 -> 8.04s on my machine, ~7%.

llvm-svn: 93200

Consolidate ConvertGlobalValIDToValue, ConvertGlobalOrMetadataValIDToValue, and ConvertValIDToValue into a more powerful ConvertValIDToValue() that does all three's work

llvm-svn: 93197

llvm-svn: 93195

Implement the same interface as already available for dominators.

llvm-svn: 93194

Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.

llvm-svn: 93191

llvm-svn: 93189

Shorten up this testcase.

llvm-svn: 93187

llvm-svn: 93185

This fixes PR5980.

llvm-svn: 93184

llvm-svn: 93183

llvm-svn: 93182

loads are not in the default address space because the transformation discards src value info.

llvm-svn: 93180

llvm-svn: 93174

llvm-svn: 93172

documentation.

Patch by Dustin Laurence!

llvm-svn: 93170

convention. 

llvm-svn: 93167

llvm-svn: 93165

have a fix.

llvm-svn: 93163

- getToken is modeled after StringRef::split but it can split on multiple
  separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
  same behaviour as getToken.

llvm-svn: 93161

has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.

llvm-svn: 93160

new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158

llvm-svn: 93157

llvm-svn: 93156

single user. The _su forms are intended for non-top-level nodes.

llvm-svn: 93155

llvm-svn: 93154

Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.

llvm-svn: 93152

Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151

Make InsertDbgValueIntrinsic() and get Offset take and recieve a uint64_t.
Get constness correct for getVariable() and getValue().

llvm-svn: 93149