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  1. Apr 02, 2013
    • Jakob Stoklund Olesen's avatar
      Add 64-bit shift instructions. · c1d1a481
      Jakob Stoklund Olesen authored
      SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
      instructions are still usable as zero and sign extensions.
      
      This adds new F3_Sr and F3_Si instruction formats that probably should
      be used for the 32-bit shifts as well. They don't really encode an
      simm13 field.
      
      llvm-svn: 178525
      c1d1a481
  2. Feb 18, 2012
  3. Dec 29, 2007
  4. Jul 19, 2007
    • Evan Cheng's avatar
      Change instruction description to split OperandList into OutOperandList and · 94b5a80b
      Evan Cheng authored
      InOperandList. This gives one piece of important information: # of results
      produced by an instruction.
      An example of the change:
      def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                       "add{l} {$src2, $dst|$dst, $src2}",
                       [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
      =>
      def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                       "add{l} {$src2, $dst|$dst, $src2}",
                       [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
      
      llvm-svn: 40033
      94b5a80b
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