- Sep 26, 2007
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Evan Cheng authored
Tested with "make check"! llvm-svn: 42346
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Chris Lattner authored
llvm-svn: 42345
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Chris Lattner authored
llvm-svn: 42344
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Chris Lattner authored
llvm-svn: 42343
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Chris Lattner authored
llvm-svn: 42342
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Chris Lattner authored
llvm-svn: 42341
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Duncan Sands authored
llvm-svn: 42338
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Evan Cheng authored
llvm-svn: 42335
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Evan Cheng authored
llvm-svn: 42333
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Anton Korobeynikov authored
llvm-svn: 42332
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Daniel Berlin authored
llvm-svn: 42331
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Dale Johannesen authored
llvm-svn: 42329
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Dale Johannesen authored
cases with undefined behavior. llvm-svn: 42328
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Chris Lattner authored
llvm-svn: 42324
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Evan Cheng authored
llvm-svn: 42323
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- Sep 25, 2007
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Anton Korobeynikov authored
llvm-svn: 42322
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Bill Wendling authored
llvm-svn: 42318
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Dan Gohman authored
llvm-svn: 42316
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Duncan Sands authored
llvm-svn: 42314
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Dan Gohman authored
llvm-svn: 42313
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Evan Cheng authored
llvm-svn: 42312
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Devang Patel authored
This fixes PR714. llvm-svn: 42309
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Dan Gohman authored
both results with a single div or idiv instruction. This uses new X86ISD nodes for DIV and IDIV which are introduced during the legalize phase so that the SelectionDAG's CSE can automatically eliminate redundant computations. llvm-svn: 42308
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Devang Patel authored
llvm-svn: 42306
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Dale Johannesen authored
llvm-svn: 42303
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Evan Cheng authored
llvm-svn: 42302
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Devang Patel authored
doh.. llvm-svn: 42300
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Devang Patel authored
for (i=A; i<N; i++) { if (i < X && i > Y) do_something(); } is transformed into U=min(N,X); L=max(A,Y); for (i=L;i<U;i++) do_somethihg(); llvm-svn: 42299
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Dale Johannesen authored
of zero, infinity, and NaNs. llvm-svn: 42298
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Dan Gohman authored
the check to see if the assembler supports .loc from X86TargetLowering into the superclass TargetLowering. llvm-svn: 42297
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Duncan Sands authored
llvm-svn: 42296
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Duncan Sands authored
llvm-svn: 42294
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Owen Anderson authored
llvm-svn: 42286
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Evan Cheng authored
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after all the kinks are worked out. llvm-svn: 42285
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Evan Cheng authored
Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered. llvm-svn: 42284
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Evan Cheng authored
llvm-svn: 42283
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Evan Cheng authored
llvm-svn: 42282
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Dale Johannesen authored
have situations where an SSE instruction turns into multiple blocks, with the live range of an x87 register crossing them. To do this correctly make sure we examine all blocks when inserting FP_REG_KILL. PR 1697. (This was exposed by my fix for PR 1681, but the same thing could happen mixing x87 long double with SSE.) llvm-svn: 42281
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Bill Wendling authored
llvm-svn: 42280
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Daniel Berlin authored
llvm-svn: 42279
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