llvm-svn: 100649

llvm-svn: 100648

llvm-svn: 100647

Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.

llvm-svn: 100646

llvm-svn: 100643

llvm-svn: 100642

llvm-svn: 100641

Radar 7770501.

llvm-svn: 100568

isn't well specified.  ARM really needs to have its instprinter
finished at some point.

llvm-svn: 100439

with spaces in them.  Sym->getName()  !=   OS << *Sym

llvm-svn: 100434

llvm-svn: 100404

  uint32_t insn;
  MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)

to read 4 bytes of memory contents into a 32-bit uint variable.  This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail.  Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.

llvm-svn: 100403

When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384

llvm-svn: 100380

llvm-svn: 100379

Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests.

llvm-svn: 100378

llvm-svn: 100377

llvm-svn: 100376

which is really a property of the section being referenced.
Add a predicate to MCSection to replace it.

Yay for reduction in magic.

llvm-svn: 100367

llvm-svn: 100358

llvm-svn: 100357

llvm-svn: 100342

enough to warrant caching in AsmPrinter, so remove it.

llvm-svn: 100336

"asm printering" happens through MCStreamer.  This also 
Streamerizes PIC16 debug info, which escaped my attention.

This removes a leak from LLVMTargetMachine of the 'legacy'
output stream.

llvm-svn: 100327

don't have mcstreamer support for yet.

llvm-svn: 100319

implementations to use EmitRawText instead of writing
directly to "O".

llvm-svn: 100318

raw_ostream to print to.

llvm-svn: 100313

raw_ostream to print an instruction to had to be specified
at MCInstPrinter construction time instead of being able
to pick at each call to printInstruction.

llvm-svn: 100307

member of AsmPrinter.  Instead, pass it in explicitly.

llvm-svn: 100306

Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304

of printOffset to pass in a stream to print to.

llvm-svn: 100296

abstraction it brings.  And also get rid of the atexit() handler, it does not
belong in the lib directory. :-)

llvm-svn: 100265

llvm-svn: 100259

occuplied by the cached ARMAlgorithm objects.

llvm-svn: 100258

llvm-svn: 100251

backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233

to the ARM AsmParser.

llvm-svn: 100232

llvm-svn: 100214

llvm-svn: 100199

Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100191