Krasin!

llvm-svn: 136663

llvm-svn: 136656

llvm-svn: 136655

the legalizer. This commit together with the two previous ones fixes
PR10495.

llvm-svn: 136654

llvm-svn: 136653

using a stack store.

llvm-svn: 136652

TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

llvm-svn: 136643

avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

llvm-svn: 136642

llvm-svn: 136639

one than one successor goes to the same block.

llvm-svn: 136638

llvm-svn: 136623

Update CMake target names for tablegen-generated data in the X86 and ARM targets. This should fix the CMake build with MSVC.

llvm-svn: 136621

llvm-svn: 136612

llvm-svn: 136611

llvm-svn: 136610

llvm-svn: 136609

them properly. Specifically, the disassembler clearly attempts to
initialiaze all TargetInfo, MCTargeDesc, AsmParser, and Disassembler
sublibraries of registered targets. This makes the CMakeLists accurately
reflect this intent in the code.

This should fix the last of the link errors that I have gotten reports
of on OS X, but if anyone continues to see link errors, continue to
pester me and I'll look into it.

llvm-svn: 136603

This adds the 'resume' instruction class, IR parsing, and bitcode reading and
writing. The 'resume' instruction resumes propagation of an existing (in-flight)
exception whose unwinding was interrupted with a 'landingpad' instruction (to be
added later).

llvm-svn: 136589

llvm-svn: 136588

llvm-svn: 136587

it to RHS anyway.

llvm-svn: 136586

llvm-svn: 136585

llvm-svn: 136584

decide whether condition is likely to be true this way:

x == 0  ->  false
x <  0  ->  false
x <= 0  ->  false
x != 0  ->  true
x >  0  ->  true
x >= 0  ->  true

llvm-svn: 136583

While this generally helped x86-64, there was some large regressions
for i386.

llvm-svn: 136571

rules to the new explicitly listed TableGen rules. Somehow I missed this
in my original sweep.

llvm-svn: 136567

r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.

llvm-svn: 136556

llvm-svn: 136552

The ARM target depends on CPSR liveness being tracked after register
allocation.

llvm-svn: 136548

This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

llvm-svn: 136541

llvm-svn: 136535

This flag is true from isel to register allocation when the machine
function is required to be in SSA form.  The TwoAddressInstructionPass
and PHIElimination passes clear the flag.

The SSA flag wil be used by the machine code verifier to check for SSA
form, and eventually an assertion can enforce it in +Asserts builds.
This will catch the common target error of creating machine code with
multiple defs of a virtual register.

llvm-svn: 136532

llvm-svn: 136529

This helps generate better code in functions with high register
pressure.

llvm-svn: 136528

Fixes rdar://9866494

llvm-svn: 136523

llvm-svn: 136510

Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509

for targets that don't have an MC-ized disassembler. I'm suspicious that
this shouldn't actually be happening, but hoping to fix the CMake build
on macs first, and investigate why second.

llvm-svn: 136508

llvm-svn: 136506

llvm-svn: 136505