llvm-svn: 135426

to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424

During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]

llvm-svn: 135423

For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.

llvm-svn: 135420

llvm-svn: 135418

moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415

Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414

When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.

We need the value number entering the instruction.

<rdar://problem/9793765>

llvm-svn: 135413

not interfere with BackedgeTakenCount computation.

llvm-svn: 135412

preheader for the sole purpose of LFTR, since LFTR itself is usually not
a clear optimization.

llvm-svn: 135409

definitions.

llvm-svn: 135407

llvm-svn: 135404

virtual registers are used. 

llvm-svn: 135403

Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.

llvm-svn: 135390

When trying to rematerialize a value before an instruction that has an
early-clobber redefine of the virtual register, make sure to look up the
correct value number.

Early-clobber defs are moved one slot back, so getBaseIndex is needed to
find the used value number.

Bugpoint was unable to reduce the test case for this, see PR10388.

llvm-svn: 135378

llvm-svn: 135375

mallocs.

llvm-svn: 135366

llvm-svn: 135364

llvm-svn: 135362

llvm-svn: 135360

llvm-svn: 135358

llvm-svn: 135354

llvm-svn: 135353

llvm-svn: 135352

llvm-svn: 135343

llvm-svn: 135339

assertion I added in r135333. Check for the existence of a preheader
before expanding a recurrence.

llvm-svn: 135335

llvm-svn: 135334

related bug fixes and corresponding assertions for uninitialized data
and missing NULL check. Test cases will be included with the new LFTR.

llvm-svn: 135333

llvm-svn: 135332

This should unbreak the build-self-4-mingw32 tester. I have a very
complicated test case that I will try to clean up.

llvm-svn: 135329

fixing some objc llvm-test crashes with LTO.

llvm-svn: 135324

llvm-svn: 135323

llvm-svn: 135320

Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135319

and just use the ones from TargetLowering directly.

llvm-svn: 135318

1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.

2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.

3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.

4) Tidy up code to be more clear and explicit about AVX.

llvm-svn: 135313

comming together with other tests.

llvm-svn: 135312

llvm-svn: 135311

This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.

Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.

llvm-svn: 135307