concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112

''const'ify getMachineOpValue() and associated helpers.'

llvm-svn: 116067

llvm-svn: 116064

llvm-svn: 116059

callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.

llvm-svn: 116055

as thumb1.

Fixes lencod.

llvm-svn: 116027

llvm-svn: 116022

llvm-svn: 116018

llvm-svn: 116002

llvm-svn: 115993

llvm-svn: 115987

llvm-svn: 115984

for them from the MCCodeEmitter.

llvm-svn: 115975

compilation of MultiSource/Benchmarks/Bullet.

llvm-svn: 115907

llvm-svn: 115906

llvm-svn: 115905

llvm-svn: 115904

llvm-svn: 115898

llvm-svn: 115890

llvm-svn: 115884

llvm-svn: 115860

Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored

llvm-svn: 115859

llvm-svn: 115853

llvm-svn: 115845

"lane" operand modifier.

llvm-svn: 115843

pseudo instructions.

llvm-svn: 115840

llvm-svn: 115831

llvm-svn: 115798

  allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755

  let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)

llvm-svn: 115720

llvm-svn: 115717

32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711

addressing mode from four to five.

llvm-svn: 115645

llvm-svn: 115594

llvm-svn: 115593

so and also change X86 for consistency.

Investigating if this can be improved a bit.

llvm-svn: 115469

1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
   dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.

llvm-svn: 115457

llvm-svn: 115390

llvm-svn: 115376

llvm-svn: 115375