llvm-svn: 68092

instructions. This fixes lua.

llvm-svn: 68083

Turn a 2-address instruction into a 3-address one when it's profitable even if the two-address operand is killed.
e.g.
%reg1024<def> = MOV r1
%reg1025<def> = ADD %reg1024, %reg1026
r0            = MOV %reg1025

If it's not possible / profitable to commute ADD, then turning ADD into a LEA saves a copy.

llvm-svn: 68065

llvm-svn: 68059

llvm-svn: 68057

llvm-svn: 68054

when using -soft-float.
Based on a patch by Jakob Stoklund Olesen.

llvm-svn: 67996

a CALL and a RET node more generic. Add a test for tail calls with a void
return.

llvm-svn: 67943

Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).

llvm-svn: 67934

Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax

llvm-svn: 67917

llvm-svn: 67881

default constructor produces an uninitialized APInt.
This fixes PR3896.

llvm-svn: 67879

llvm-svn: 67828

llvm-svn: 67764

llvm-svn: 67742

Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.

llvm-svn: 67701

stoppoint nodes around until Legalize; doing this
imposed an ordering on a sequence of loads that
came from different lines, interfering with scheduling.

llvm-svn: 67692

llvm-svn: 67668

llvm-svn: 67661

llvm-svn: 67649

the target constraint specifies a specific physreg.

llvm-svn: 67618

llvm-svn: 67617

fail.

llvm-svn: 67616

canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.

llvm-svn: 67587

help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.

llvm-svn: 67586

llvm-svn: 67580

Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.                                                                                                  
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.

llvm-svn: 67574

same as a normal i80 {low64, high16} rather
than its own {high64, low16}.  A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.

llvm-svn: 67562

a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.

And add a few comments.

llvm-svn: 67554

llvm-svn: 67544

actually have uses, which reflects the way it's used.

llvm-svn: 67540

in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.

llvm-svn: 67531

defs, regardless of whether they are actually used.

llvm-svn: 67528

explicitly flush it.

llvm-svn: 67526

Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.

llvm-svn: 67512

Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.

llvm-svn: 67511

llvm-svn: 67400

For inline asm output operand that matches an input. Encode the input operand index in the high bits.

llvm-svn: 67387

llvm-svn: 67372

llvm-svn: 67370