llvm-svn: 27359

llvm-svn: 27351

llvm-svn: 27348

"vspltisb v0, 8" instead of a constant pool load.

llvm-svn: 27335

llvm-svn: 27331

llvm-svn: 27322

No functionality change.

llvm-svn: 27320

llvm-svn: 27315

llvm-svn: 27308

llvm-svn: 27307

llvm-svn: 27306

llvm-svn: 27305

llvm-svn: 27302

llvm-svn: 27291

identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll

llvm-svn: 27290

llvm-svn: 27288

llvm-svn: 27287

predicates to VCMPo nodes.

llvm-svn: 27285

llvm-svn: 27284

llvm-svn: 27276

llvm-svn: 27268

directly correspond to intrinsics.

llvm-svn: 27266

llvm-svn: 27265

llvm-svn: 27243

llvm-svn: 27227

llvm-svn: 27225

llvm-svn: 27216

llvm-svn: 27215

llvm-svn: 27209

same thing and we have a dag node for the former.

llvm-svn: 27205

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.

llvm-svn: 27201

llvm-svn: 27180

llvm-svn: 27170

llvm-svn: 27168

llvm-svn: 27160

llvm-svn: 27159

manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156

llvm-svn: 27153

llvm-svn: 27151

llvm-svn: 27149