order, causing the inactive list in the linearscan list to get unsorted, which
basically fuxored everything up severely.

These seems to fix the joiner, so with more testing I will enable it by default.

llvm-svn: 14992

Heavily refactor handleVirtualRegisterDef, adding comments and making it more
efficient.  It is also much easier to follow and convince ones self that it is
correct :)

Add -debug output to the joine, showing the result of joining the intervals.

llvm-svn: 14989

but make virtreg->virtreg joining stay off by default

llvm-svn: 14916

llvm-svn: 14720

llvm-svn: 14719

llvm-svn: 14655

classes: just ignore that move. Thanks to Vladimir Prus who found the
bug!

llvm-svn: 14644

don't exist, we don't have to pretend to handle them.

llvm-svn: 14567

use them instead of a local LiveVariables numbering

llvm-svn: 14523

map.

llvm-svn: 14518

llvm-svn: 14475

llvm-svn: 14474

Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.

llvm-svn: 14389

existing llvm::Interval class.

Patch contributed by Vladimir Prus!
http://mail.cs.uiuc.edu/pipermail/llvmbugs/2004-June/000710.html

llvm-svn: 14281

llvm-svn: 13956

llvm-svn: 13910

spills. This allows for more flexibility when allocating registers for
spill code.

llvm-svn: 13907

llvm-svn: 13892

llvm-svn: 13416

workaround, use the C HUGE_VAL macro instead.

llvm-svn: 13377

llvm-svn: 13302

llvm-svn: 12872

llvm-svn: 12869

llvm-svn: 12866

llvm-svn: 12791

instruction to make the API more flexible.

llvm-svn: 12386

llvm-svn: 12058

MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.

llvm-svn: 11882

llvm-svn: 11721

llvm-svn: 11719

llvm-svn: 11704

Also make it less aggressive as the current implementation breaks in
some cases.

llvm-svn: 11696

llvm-svn: 11687

llvm-svn: 11676

llvm-svn: 11675

llvm-svn: 11674

1. LiveIntervals now implement a 4 slot per instruction model. Load,
   Use, Def and a Store slot. This is required in order to correctly
   represent caller saved register clobbering on function calls,
   register reuse in the same instruction (def resues last use) and
   also spill code added later by the allocator. The previous
   representation (2 slots per instruction) was insufficient and as a
   result was causing subtle bugs.

2. Fixes in spill code generation. This was the major cause of
   failures in the test suite.

3. Linear scan now has core support for folding memory operands. This
   is untested and not enabled (the live interval update function does
   not attempt to fold loads/stores in instructions).

4. Lots of improvements in the debugging output of both live intervals
   and linear scan. Give it a try... it is beautiful :-)

In summary the above fixes all the issues with the recent reserved
register elimination changes and get the allocator very close to the
next big step: folding memory operands.

llvm-svn: 11654

llvm-svn: 11575

llvm-svn: 11574

llvm-svn: 11516