llvm-svn: 164087

llvm-svn: 164086

start of a statement or the end of a compound-statement, diagnose the comma as
a typo for a semicolon. Patch by Ahmed Bougacha! Additional test cases and
minor refactoring by me.

llvm-svn: 164085

and a conditional branch; also when removing dead cases from a switch.

llvm-svn: 164084

is no compelling argument that this is a generally useful warning,
and imposes a strong stylistic argument on code beyond what it was
intended to find warnings in.

llvm-svn: 164083

Making ClangExpression hold on to a WP to the Process instead of a SP. This fix should enable us to have per-process maps of ClangExpressions without fear of keeping the process alive forever

llvm-svn: 164082

llvm-svn: 164081

missing 'assign' attribute as it is determined by its
overridden property in primary class. // rdar://12214070 

llvm-svn: 164080

llvm-svn: 164079

llvm-svn: 164078

argument names. // rdar://12263549

llvm-svn: 164077

Hanlde the case when we split the default edge if the default target has "icmp"
and unconditinal branch.

llvm-svn: 164076

llvm-svn: 164075

Add LIS::pruneValue() and extendToIndices(). These two functions are
used by the register coalescer when merging two live ranges requires
more than a trivial value mapping as supported by LiveInterval::join().

The pruneValue() function can remove the part of a value number that is
going to conflict in join(). Afterwards, extendToIndices can restore the
live range, using any new dominating value numbers and updating the SSA
form.

Use this complex value mapping to support merging a register into a
vector lane that has a conflicting value, but the clobbered lane is
undef.

llvm-svn: 164074

These extra operands are not needed by register allocators using
VirtRegRewriter, and RAFast don't need them any longer.

By omitting the <imp-def> operands, it becomes possible for the new
register coalescer to track which lanes are valid and which are undef.

llvm-svn: 164073

I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072

llvm-svn: 164071

llvm-svn: 164070

llvm-svn: 164068

llvm-svn: 164067

llvm-svn: 164066

llvm-svn: 164065

llvm-svn: 164064

llvm-svn: 164063

TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.

llvm-svn: 164062

llvm-svn: 164061

llvm-svn: 164060

Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

llvm-svn: 164059

llvm-svn: 164058

llvm-svn: 164057

While we are setting the earlier def to true, also make it live.

llvm-svn: 164056

llvm-svn: 164055

destination in SimplifyCondBranchToCondBranch.

llvm-svn: 164054

checking on property declared in class extension.
// rdar://12214070

llvm-svn: 164053

llvm-svn: 164052

we will do that when we implement the full save/restore.

Patch by Reed Kotler.

llvm-svn: 164051

llvm-svn: 164050

stomped on.

llvm-svn: 164049

llvm-svn: 164048

between objc method parameter name and colon.
// rdar://12263549

llvm-svn: 164047