llvm-svn: 130931

Avoid extra vreg copies for arguments passed in registers.  Specifically, this can make MachineCSE more effective in some cases (especially in small functions).  PR8361 / part of rdar://problem/8259436 .

llvm-svn: 130928

This should unbreak llvm-gcc-i386-linux-selfhost.

llvm-svn: 130927

llvm-svn: 130926

llvm-svn: 130925

llvm-svn: 130920

who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>

llvm-svn: 130918

llvm-svn: 130915

llvm-svn: 130914

crash.

llvm-svn: 130911

llvm-svn: 130903

filename.

llvm-svn: 130897

Joining physregs is inherently dangerous because it uses a heuristic to avoid
creating invalid code. Linear scan had an emergency spilling mechanism to deal
with those rare cases. The new greedy allocator does not.

The greedy register allocator is much better at taking hints, so this has almost
no impact on code size and quality. The few cases where it matters show up as
unit tests that now have -join-physregs enabled explicitly.

llvm-svn: 130896

llvm-svn: 130895

llvm-svn: 130894

llvm-svn: 130893

It is OK for B to be any GR8_ABCD_H superclass, the returned register class
doesn't have to map surjectively onto B.

llvm-svn: 130892

Most of these tests require a single mov instruction that can come either before
or after a 2-addr instruction. -join-physregs changes the behavior, but the
results are equivalent.

llvm-svn: 130891

llvm-svn: 130889

llvm-svn: 130885

the default register allocator is changed.

llvm-svn: 130883

landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>

llvm-svn: 130881

llvm-svn: 130880

That's kinda weird because the .gcno files are supposed to already be there,
but libgcov does this and somehow Google has managed to depend on it.

llvm-svn: 130879

Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130877

llvm-svn: 130876

This test fails on ARM. The test shouldn't explicitly specify alignment (and alignment 4 is wrong) and requires hard-float.

llvm-svn: 130875

If builder is initialized using an instruction as insertion point, then use the instruction's debug location as current debug location.

llvm-svn: 130874

llvm-svn: 130869

llvm-svn: 130867

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130862

llvm-svn: 130860

llvm-svn: 130859

These tests all follow the same pattern:

	mov	r2, r0
	movs	r0, #0
	$CMP	r2, r1
	it	eq
	moveq	r0, #1
	bx	lr

The first 'mov' can be eliminated by rematerializing 'movs r0, #0' below the
test instruction:

	$CMP	r0, r1
	mov.w	r0, #0
	it	eq
	moveq	r0, #1
	bx	lr

So far, only physreg coalescing can do that. The register allocators won't yet
split live ranges just to eliminate copies. They can learn, but this particular
problem is not likely to show up in real code. It only appears because r0 is
used for both the function argument and return value.

llvm-svn: 130858

llvm-svn: 130857

llvm-svn: 130856

llvm-svn: 130855

llvm-svn: 130854

llvm-svn: 130850

llvm-svn: 130849