code in one place.

llvm-svn: 131534

than either the primitive size or the element primitive size (in the case
of vectors), simplify the vector logic.  No functionality change.  There
is some distracting churn in the patch because I lined up comments better
while there - sorry about that.

llvm-svn: 131533

happily accept things like "sext <2 x i32> to <999 x i64>".  It would
also accept "sext <2 x i32> to i64", though the verifier would catch
that later.  Fixed by having castIsValid check that vector lengths match
except when doing a bitcast.  (2) When creating a cast instruction, check
that the cast is valid (this was already done when creating constexpr
casts).  While there, replace getScalarSizeInBits (used to allow more
vector casts) with getPrimitiveSizeInBits in getCastOpcode and isCastable
since vector to vector casts are now handled explicitly by passing to the
element types; i.e. this bit should result in no functional change.

llvm-svn: 131532

can be used to turn a <4 x i64> into a <4 x i32> but getCastOpcode would assert
if you passed these types to it.  Note that this strictly extends the previous
functionality: if getCastOpcode previously accepted two vector types (i.e. didn't
assert) then it still will and returns the same opcode (BitCast).  That's because
before it would only accept vectors with the same bitwidth, and the new code only
touches vectors with the same length.  However if two vectors have both the same
bitwidth and the same length then their element types have the same bitwidth, so
the new logic will return BitCast as before.

llvm-svn: 131530

In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529

GAS has no such directives (not even mingw-w64 GAS has them), so I took
creative license with their names in assembly. I prefixed them all with
"w64_" to avoid namespace collisions, for example. If I discover that GAS
has taken a different approach, I'll change ours to match.

llvm-svn: 131525

llvm-svn: 131524

The 'last use' may not be in the same basic block, and we still want a correct
live range.

llvm-svn: 131523

the purposes of the Win64 EH tables, I realized we had no way to tell where
the function ends. (MASM bounds functions with PROC and ENDP keywords.)
Add a directive to delimit the end of the function, and rename the 'frame'
directive to more accurately reflect its duality with the new directive.

llvm-svn: 131522

LiveInterval::shrinkToUses recomputes the live range from scratch instead of
removing snippets. This should avoid the problem with dangling live ranges.

Leave physreg identity copies alone. They can be created when joining a virtreg
with a physreg. They don't affect register allocation, and they will be removed
by the rewriter.

llvm-svn: 131521

llvm-svn: 131519

compare-and-swap intrinsics.

llvm-svn: 131518

Start trying to make InstCombine preserve more debug info.  The idea here is to set the debug location on the IRBuilder, which will be then right location in most cases.  This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder.

As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten.

Chris, does this approach look reasonable?

llvm-svn: 131516

llvm-svn: 131512

llvm-svn: 131508

take r13, so we can just make it a GPR. This fixes PR8825.

llvm-svn: 131507

were marked as taking a tGPR when in reality they take an rGPR.

llvm-svn: 131506

format.

llvm-svn: 131503

Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant.

llvm-svn: 131502

llvm-svn: 131497

llvm-svn: 131495

rdar://problem/6945110

llvm-svn: 131493

vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.

llvm-svn: 131488

llvm-svn: 131482

llvm-svn: 131481

llvm-svn: 131480

llvm-svn: 131476

This is r131438 with a couple small fixes.

llvm-svn: 131474

llvm-svn: 131471

llvm-svn: 131469

passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088

llvm-svn: 131467

The greedy register allocator has live range splitting and register class
inflation, so it can actually fully undo this join, including restoring the
original register classes.

We still don't want to do this for long live ranges, mostly because of the high
register pressure of there are many constrained live ranges overlapping.

llvm-svn: 131466

getHostTriple. This fixes a 32 bit clang running on a 64 bit ubuntu.

llvm-svn: 131463

Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
with two different types, in cases where the index and the ptr had different
types.

llvm-svn: 131461

llvm-svn: 131459

Finishes off rdar://8470697

llvm-svn: 131458

llvm-svn: 131457

llvm-svn: 131456

llvm-svn: 131455

it more tomorrow.

llvm-svn: 131451