Commits · c5e0ed109d002326fa90a3ff5054b0f49821b374 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Mar 01, 2018
- [Hexagon] Add trap1 instruction · c5e0ed10
  Krzysztof Parzyszek authored Mar 01, 2018
  c5e0ed10
- Add an llc testcase analogous to test/LTO/X86/strip-debug-info.ll · 17dd0edf
  Adrian Prantl authored Mar 01, 2018
  17dd0edf
- AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtz · 364f12e8
  Matt Arsenault authored Mar 01, 2018
  364f12e8
- AMDGPU/GlobalISel: Define instruction mapping for G_OR · 5320ee4a
  Matt Arsenault authored Mar 01, 2018
  5320ee4a
- [X86][SSE] Regenerate float to/from i8/i16 vector tests · c6f4a6a0
  Simon Pilgrim authored Mar 01, 2018
  c6f4a6a0
- [X86][SSE] Regenerate odd sized sext/zext tests · 94ea374b
  Simon Pilgrim authored Mar 01, 2018
  94ea374b
- AMDGPU/GlobalISel: Define instruction mapping for G_BITCAST · 62669ede
  Matt Arsenault authored Mar 01, 2018
  62669ede
- AMDGPU/GlobalISel: Mark i32->i64 zext as legal · 0529a8e2
  Matt Arsenault authored Mar 01, 2018
  0529a8e2
- [AArch64] Add support for secrel add/load/store relocations for COFF · c61ff3be
  Martin Storsjo authored Mar 01, 2018
  c61ff3be
- AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.compr · 36b99e19
  Matt Arsenault authored Mar 01, 2018
  36b99e19
- AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.exp · 8931bbf8
  Matt Arsenault authored Mar 01, 2018
  8931bbf8
- [InstCombine] Auto-generate complete checks. NFC · f1a7c675
  Craig Topper authored Mar 01, 2018
  f1a7c675
- AMDGPU/GlobalISel: Define InstrMappings for G_ICMP · 50721ab3
  Matt Arsenault authored Mar 01, 2018
  50721ab3
- AMDGPU/GlobalISel: Make i32 mul legal · dc14ec05
  Matt Arsenault authored Mar 01, 2018
  dc14ec05
- AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEF · 06cbb27a
  Matt Arsenault authored Mar 01, 2018
  06cbb27a
- AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANT · e3d9ecf2
  Matt Arsenault authored Mar 01, 2018
  e3d9ecf2
- AMDGPU/GlobalISel: Make i32 xor legal · 3f6a204e
  Matt Arsenault authored Mar 01, 2018
  3f6a204e
- AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legal · 8e80a5fb
  Matt Arsenault authored Mar 01, 2018
  8e80a5fb
- AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legal · dd022ce0
  Matt Arsenault authored Mar 01, 2018
  dd022ce0
- [Hexagon] Add guest registers · 22a21d4c
  Krzysztof Parzyszek authored Mar 01, 2018
  22a21d4c
- [InstCombine] remove stale comments for tests; NFC · d696e93c
  Sanjay Patel authored Mar 01, 2018
  d696e93c
- [WebAssembly] Update pre-generated test files to match latest llc output. NFC. · f6be8e8c
  Nicholas Wilson authored Mar 01, 2018
  f6be8e8c
- [AArch64] generate vuzp instead of mov · c33af715
  Sebastian Pop authored Mar 01, 2018
  c33af715
- [InstCombine] move/add tests for fmul reassociation; NFC · 3fd43a84
  Sanjay Patel authored Mar 01, 2018
  3fd43a84
- [InstCombine] auto-generate full checks; NFC · 237e5267
  Sanjay Patel authored Mar 01, 2018
  237e5267
- Revert "[DEBUGINFO] Add flag for DWARF2 or less to use sections as references." · d7c6fdbc
  Alexey Bataev authored Mar 01, 2018
  d7c6fdbc
- [CodeGen] fix argument attribute in lowering statepoint/patchpoint · b3d88a74
  Than McIntosh authored Mar 01, 2018
  b3d88a74
- [SCEV] Smart range calculation for SCEVUnknown Phis · f8d2969a
  Max Kazantsev authored Mar 01, 2018
  f8d2969a
- [RuntimeDyld][MachO] Fix assertion in encodeAddend, add missing directive to · 811343cf
  Lang Hames authored Mar 01, 2018
  811343cf
- [IPSCCP] do not break musttail invariant (PR36485) · 3762a089
  Reid Kleckner authored Mar 01, 2018
  3762a089
- [GlobalISel][AArch64] Adding -disable-gisel-legality-check CL option · 2b94972e
  Roman Tereshin authored Mar 01, 2018
  2b94972e
- [DWARF] Emit a split line table only if there are split type units. · 1e0116c9
  Paul Robinson authored Mar 01, 2018
  1e0116c9
- [DAE] don't remove args of musttail target/caller · cb9611ca
  Reid Kleckner authored Mar 01, 2018
  cb9611ca
- [X86] Make sure we don't combine (fneg (fma X, Y, Z)) to a target specific... · ccfa5257
  Craig Topper authored Mar 01, 2018
  ccfa5257
- [NVPTX] Lower loads from global constants using ld.global.nc (aka LDG). · faaf2d29
  Justin Lebar authored Feb 28, 2018
  faaf2d29
- [NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM. · 5a7de898
  Justin Lebar authored Feb 28, 2018
  5a7de898
- [MIRParser] Accept overloaded intrinsic names w/o type suffixes · 12a4dc4c
  Roman Tereshin authored Feb 28, 2018
  12a4dc4c
Feb 28, 2018
- [X86] Regenerate cmpxchg tests · c38756a9
  Simon Pilgrim authored Feb 28, 2018
  c38756a9
- [InstCombine] simplify code for X * -1.0 --> -X; NFC · eaf5a120
  Sanjay Patel authored Feb 28, 2018
  eaf5a120
- [GlobalOpt] don't change CC of musttail calle(e|r) · 9ca06455
  Jonas Devlieghere authored Feb 28, 2018
  9ca06455