It is both smaller and faster than DenseMap.

llvm-svn: 159029

llvm-svn: 159028

Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027

EmitZerofill should take a 64-bit size or else it's chopping off large zero-filled global. rdar://11729134

llvm-svn: 159023

Don't try to print out the live range of a physreg.

llvm-svn: 159021

DBG_VALUE instructions could be referring to non-existing virtual
registers.

llvm-svn: 159020

There is no need to check for physreg live ranges. They don't exist any
more.

llvm-svn: 159019

Everyone is using on-demand regunit ranges now.

llvm-svn: 159018

llvm-svn: 159017

These functions only operate on virtual registers now, and they all have
live ranges.

llvm-svn: 159015

llvm-svn: 159014

Don't depend on LiveIntervals::hasInterval() to determine if a physreg
is reserved and constant.

llvm-svn: 159013

llvm-svn: 159011

This should produce the same results as using physreg liveness directly.

llvm-svn: 159009

With regunit liveness permanently enabled, this function would always
return true.

Also remove now obsolete code for checking physreg interference.

llvm-svn: 159006

This fixes PR5997.

These transforms were disabled because codegen couldn't deal with other
uses of trunc(x). This is now handled by the peephole pass.

This causes no regressions on x86-64.

llvm-svn: 159003

llvm-svn: 159000

llvm-svn: 158999

Original message:
Performance optimizations:
- SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges.
- Optimized IntItem, added APInt value caching.
- Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only.

llvm-svn: 158997

llvm-svn: 158994

knows dwarf or not.

llvm-svn: 158993

DwarfUsesRelocationsAcrossSections.

llvm-svn: 158992

fail.  Original commit message:

Performance optimizations:
- SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges.
- Optimized IntItem, added APInt value caching.
- Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only.

On my machine these optimizations gave about 4-6% of compile-time improvement.

llvm-svn: 158986

- SwitchInst: case values stored separately from Operands List. It allows to make faster access to individual case value numbers or ranges.
- Optimized IntItem, added APInt value caching.
- Optimized IntegersSubsetGeneric: added optimizations for cases when subset is single number or when subset consists from single numbers only.

On my machine these optimizations gave about 4-6% of compile-time improvement.

llvm-svn: 158979

This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963

The code in X86TargetLowering::LowerEH_RETURN() assumes that a frame
pointer exists, but the frame pointer was forced by the presence of
llvm.eh.unwind.init which isn't guaranteed.

If llvm.eh.unwind.init is actually required in functions calling
eh.return (is it?), we should diagnose that instead of emitting bad
machine code.

This should fix the dragonegg-x86_64-linux-gcc-4.6-test bot.

llvm-svn: 158961

This is a minor drive-by fix with no robust way to unit test.
As an example see neon-div.ll:
SU(16):   %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill>
 val SU(1): Latency=2 Reg=%Q8
...should be latency=1

llvm-svn: 158960

Minor drive by fix to cleanup latency computation. Calling
getOperandLatency with a deliberately incorrect operand index does not
give you the latency you want.

llvm-svn: 158959

a recommit of r127757. Fixes PR9493. Patch by Paul Robinson!

llvm-svn: 158957

boolean flag to an enum: { Fast, Standard, Strict } (default = Standard).

This option controls the creation by optimizations of fused FP ops that store
intermediate results in higher precision than IEEE allows (E.g. FMAs). The
behavior of this option is intended to match the behaviour specified by a
soon-to-be-introduced frontend flag: '-ffuse-fp-ops'.

Fast mode - allows formation of fused FP ops whenever they're profitable.

Standard mode - allow fusion only for 'blessed' FP ops. At present the only
blessed op is the fmuladd intrinsic. In the future more blessed ops may be
added.

Strict mode - allow fusion only if/when it can be proven that the excess
precision won't effect the result.

Note: This option only controls formation of fused ops by the optimizers.  Fused
operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic)
will always be honored, regardless of the value of this option.

Internally TargetOptions::AllowExcessFPPrecision has been replaced by
TargetOptions::AllowFPOpFusion.

llvm-svn: 158956

The existing contraction patterns are replaced with fma/fneg.
Overall functionality should be the same.

llvm-svn: 158955

sorry for the churn :S  enough for today; going to sleep.

llvm-svn: 158953

remove extractMallocCallFromBitCast, since it was tailor maded for its sole user. Update GlobalOpt accordingly.

llvm-svn: 158952

instcombine:  disable optimization of 'invoke null/undef'. I'll move this functionality to SimplifyCFG (since we cannot make changes to the CFG here).
Fixes the crashes with the attached test case

llvm-svn: 158951

llvm-svn: 158947

llvm-svn: 158946

llvm-svn: 158943

llvm-svn: 158942

llvm-svn: 158941

to be generic across architectures. It has the
following description in the gnu sources:

    Negate the immediate constant

Several Architectures such as x86 have local implementations
of operand modifier 'n' which go beyond the above description
slightly. This won't affect them.

Affected files:

    lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
        Added 'n' to the switch cases.

    test/CodeGen/Generic/asm-large-immediate.ll
        Generic compiled test (x86 for me)

    test/CodeGen/Mips/asm-large-immediate.ll
        Mips compiled version of the generic one

Contributer: Jack Carter
llvm-svn: 158939