llvm-svn: 138623

I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621

SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between.

In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.

This shrinks the size of a Release clang by 16k on x86_64.

llvm-svn: 138618

llvm-svn: 138606

llvm-svn: 138588

Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

proper function to do it.

llvm-svn: 138550

llvm-svn: 138546

llvm-svn: 138541

llvm-svn: 138539

Hook up 64-bit atomic load/store on x86-32.  I plan to write more efficient implementations eventually.

llvm-svn: 138505

.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184

llvm-svn: 138504

llvm-svn: 138502

Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494

Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488

llvm-svn: 138486

llvm-svn: 138469

llvm-svn: 138441

variable sized alloca.

llvm-svn: 138433

Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.

llvm-svn: 138427

permutations. Also tidy up some patterns and make them close to their
instruction definition!

llvm-svn: 138392

This reverts commit 20a05be15ea5271ab6185b83200fa88263362400. (svn rev 138340)

Conflicts:

	test/Transforms/InstCombine/bitcast.ll

llvm-svn: 138366

llvm-svn: 138364

llvm-svn: 138363

llvm-svn: 138362

llvm-svn: 138361

llvm-svn: 138360

llvm-svn: 138359

llvm-svn: 138354

llvm-svn: 138352

llvm-svn: 138349

llvm-svn: 138348

Not including tSTRspi.

llvm-svn: 138347

llvm-svn: 138345

llvm-svn: 138342

Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

llvm-svn: 138341

1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector

llvm-svn: 138340