llvm-svn: 88921

conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874

llvm-svn: 88817

llvm-svn: 88734

Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.

llvm-svn: 86997

llvm-svn: 86984

llvm-svn: 86972

  cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
  later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
  users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
  iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.

llvm-svn: 86969

tail merging support to handle more cases.
 - Recognize several cases where tail merging is beneficial even when
   the tail size is smaller than the generic threshold.
 - Make use of MachineInstrDesc::isBarrier to help detect
   non-fallthrough blocks.
 - Check for and avoid disrupting fall-through edges in more cases.

llvm-svn: 86871

llvm-svn: 86614

llvm-svn: 86494

llvm-svn: 86330

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

llvm-svn: 86298

llvm-svn: 85986

llvm-svn: 85871

llvm-svn: 85848

llvm-svn: 85787

llvm-svn: 85743

llvm-svn: 85723

llvm-svn: 85698

them for scalar floating point operations for now.

llvm-svn: 85697

llvm-svn: 85696

llvm-svn: 85695

llvm-svn: 85694

llvm-svn: 85693

llvm-svn: 85691

llvm-svn: 85676

llvm-svn: 85674

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

llvm-svn: 85210

llvm-svn: 85051

llvm-svn: 85050

immediate operands when they will fit into the using instruction.

llvm-svn: 84778

llvm-svn: 84751

llvm-svn: 84727

llvm-svn: 84658

llvm-svn: 84212

llvm-svn: 83241