llvm-svn: 128503

was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134

llvm-svn: 128502

llvm-svn: 128501

Fill in code in EmulateADDRegShift, to emulate the ADD
(register-shifted register) ARM instruction.

llvm-svn: 128500

llvm-svn: 128499

llvm-svn: 128498

llvm-svn: 128497

On x86 we now compile "if (a < 0 && b < 0)" into
	testl	%edi, %esi
	js	IF.THEN

llvm-svn: 128496

llvm-svn: 128495

llvm-svn: 128494

Can't just call "rand" to get a random port, 'cause then you'll get the same sequence in two lldb's.  This makes running lldb on lldb not work very well.  

llvm-svn: 128493

<rdar://problem/8875309> and <rdar://problem/9057191>.

llvm-svn: 128492

Add subtraction context.

Add code to emulate SUB (SP minus register) ARM instruction.

Add stubs for other ARM emulation functions that need to be written.

llvm-svn: 128491

The spill weight is not recomputed for an unspillable register - it stays infinite.

llvm-svn: 128490

  - Also emit a list of packages and groups sorted by name
  - Avoid iterating over DenseSet so that the output of the arrays is deterministic.

llvm-svn: 128489

and Nans with the same strings as GAS supports.  rdar://8673024

llvm-svn: 128488

llvm-svn: 128487

llvm-svn: 128486

llvm-svn: 128485

unnecesary conditionals and introduced a new convenience function.

The problem was that the list of libraries for Clang's unit tests was
<clang libraries> <system libraries> <llvm libraries>. As the llvm
libraries references symbols defined on the system libraries, those
were reported as undefined.

llvm-svn: 128484

llvm-svn: 128483

Fixes PR9569 and will hopefully make selfhost on ASLR-enabled systems more deterministic.

llvm-svn: 128482

Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.

llvm-svn: 128481

llvm-svn: 128480

Add missing encodings for EmulateMOVRdImm  (MOV register) function.

llvm-svn: 128479

The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.

rdar://problem/9200661

llvm-svn: 128478

llvm-svn: 128477

llvm-svn: 128476

llvm-svn: 128475

For ClangSACheckersEmitter, allow a package to belong to checker group, in which all its checkers will go into the group.

llvm-svn: 128474

assert-less codepath marginally more efficient.

llvm-svn: 128472

Do not line number entry for unconditional branches. Usually, users do not want to stop at closing '}'.

llvm-svn: 128471

llvm-svn: 128470

llvm-svn: 128469

This may eliminate some uses of the spilled registers, and we don't want to
insert reloads for that.

llvm-svn: 128468

llvm-svn: 128467

llvm-svn: 128466

llvm-svn: 128465

llvm-svn: 128461

llvm-svn: 128459