parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970

the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967

operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944

llvm-svn: 11933

llvm-svn: 11932

an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931

instructions.

llvm-svn: 11923

them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922

llvm-svn: 11921

instructions.

llvm-svn: 11907

llvm-svn: 11905

llvm-svn: 11903

consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902

llvm-svn: 11722

llvm-svn: 11576

llvm-svn: 11558

llvm-svn: 11556

llvm-svn: 11550

llvm-svn: 11549

MOVSX, and MOVZX.

llvm-svn: 11546

llvm-svn: 11544

llvm-svn: 11543

llvm-svn: 11540

order in the correct sense!! Arg!

llvm-svn: 11530

'ri' ordering instead... no it's not possible to store a register into an
immediate!

llvm-svn: 11529

llvm-svn: 11527

llvm-svn: 11521

instructions.  Add forms of these instructions that read from memory

llvm-svn: 11518

llvm-svn: 11510

llvm-svn: 11502

llvm-svn: 11451

llvm-svn: 11443

llvm-svn: 11441

generating the llvm.memcpy intrinsic.

llvm-svn: 11351

to be the same (IOW they are not two address instructions).

llvm-svn: 11117

llvm-svn: 11095

llvm-svn: 11081

llvm-svn: 11078

instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.

llvm-svn: 10562

llvm-svn: 9321