parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135

latencies) of loads.

llvm-svn: 118134

llvm-svn: 118126

llvm-svn: 118121

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

llvm-svn: 118103

llvm-svn: 118099

is handled with the MC encoder.

llvm-svn: 118098

Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.

llvm-svn: 118097

with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094

llvm-svn: 118093

llvm-svn: 118087

llvm-svn: 118084

llvm-svn: 118082

llvm-svn: 118069

llvm-svn: 118068

llvm-svn: 118067

llvm-svn: 118055

llvm-svn: 118053

llvm-svn: 118029

assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026

llvm-svn: 117997

handling those cases for now.

llvm-svn: 117996

llvm-svn: 117995

to what someone would need to do to support thumb1.

llvm-svn: 117994

since we can neither generate nor parse them at the moment.

llvm-svn: 117988

llvm-svn: 117986

llvm-svn: 117984

for handling the fixup necessary.

llvm-svn: 117978

llvm-svn: 117977

This is another part of the fix for Radar 8599955.

llvm-svn: 117976

llvm-svn: 117971

llvm-svn: 117969

llvm-svn: 117964

llvm-svn: 117956

at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950

llvm-svn: 117940

llvm-svn: 117936

codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931