llvm-svn: 168388

llvm-svn: 168359

llvm-svn: 168240

llvm-svn: 168230

style requirement.

llvm-svn: 168229

This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.

llvm-svn: 168207

This fixes PR14359

llvm-svn: 168200

An alias to a function should use pc relative addressing.

llvm-svn: 168199

llvm-svn: 168198

A PR is being filed to address some code issues here.

llvm-svn: 168185

llvm-svn: 168166

llvm-svn: 168141

allowed in branch delay slot.

llvm-svn: 168131

case to vector legalization so this actually works.

Patch by Pete Couperus.  Fixes PR12540.

llvm-svn: 168107

support and use it in place of HasMips32r2Or64.

llvm-svn: 168089

 
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.

llvm-svn: 168086

llvm-svn: 168078

llvm-svn: 168076

llvm-svn: 168064

llvm-svn: 168049

llvm-svn: 168030

llvm-svn: 168029

Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail.

llvm-svn: 168028

llvm-svn: 168025

llvm-svn: 168006

llvm-svn: 168001

Approved by Chris Lattner.

llvm-svn: 167984

llvm-svn: 167976

llvm-svn: 167974

The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.

Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.

Effectively reverts r58317. Part of PR2962.

llvm-svn: 167967

The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number.
This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.

rdar://12028498

llvm-svn: 167963

Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8

Fixes PR13291

llvm-svn: 167948

When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

llvm-svn: 167937

llvm-svn: 167922

llvm-svn: 167916

Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector.

llvm-svn: 167914

Do some cleanup of the code while here.

Inspired by patch by Logan Chien!

llvm-svn: 167904

generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.

llvm-svn: 167864

 - lwaux
 - lhzux
 - stbu

llvm-svn: 167863

operand field name mismatches in:
 - AForm_3  (fmul, fmuls)
 - XFXForm_5 (mtcrf)
 - XFLForm (mtfsf)

llvm-svn: 167862