we want to canonicalize the other way.

llvm-svn: 26547

llvm-svn: 26503

llvm-svn: 26442

PowerPC/div-2.ll

llvm-svn: 26392

on PowerPC/small-arguments.ll

llvm-svn: 26389

simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 26388

assertzext produces zero bits.

llvm-svn: 26386

llvm-svn: 26345

llvm-svn: 26317

llvm-svn: 26308

llvm-svn: 26305

that the shift may be more easily folded into other operations.

llvm-svn: 26286

llvm-svn: 26252

and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238

llvm-svn: 26174

llvm-svn: 25951

llvm-svn: 25946

llvm-svn: 25945

llvm-svn: 25900

Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use.

llvm-svn: 25866

Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler.

llvm-svn: 25803

llvm-svn: 25798

llvm-svn: 25783

llvm-svn: 25660

llvm-svn: 25609

llvm-svn: 25607

llvm-svn: 24922

* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921

llvm-svn: 24877

and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511

generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482

Add a new flag to TargetLowering indicating if the target has really cheap
  signed division by powers of two, make ppc use it.  This will probably go
  away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.

llvm-svn: 23853

llvm-svn: 23480

them more clearly.

llvm-svn: 23118

llvm-svn: 23010

This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.

llvm-svn: 22468

llvm-svn: 21422

range.  Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).

This defaults to undefined, which is conservatively correct.

llvm-svn: 19677

llvm-svn: 19619

llvm-svn: 19610