better.

Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.

llvm-svn: 139453

such.

I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.

llvm-svn: 139450

  assert("error");

to:

  assert(0 && "error");

llvm-svn: 139449

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

llvm-svn: 139432

llvm-svn: 139431

llvm-svn: 139429

llvm-svn: 139422

llvm-svn: 139421

llvm-svn: 139420

llvm-svn: 139419

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

llvm-svn: 139412

Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type.  Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs.  Fixes PR10897.

llvm-svn: 139407

llvm-svn: 139405

Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

llvm-svn: 139400

llvm-svn: 139399

the instruction.

llvm-svn: 139398

llvm-svn: 139389

llvm-svn: 139383

llvm-svn: 139381

In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs.  When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.

This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early.  This speeds up
spilling by 20x in one interpreter test case.  For more typical code,
this is just a 10% speedup of spilling.

The previous version had bugs that caused miscompilations. They have
been fixed.

llvm-svn: 139378

llvm-svn: 139375

Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.

llvm-svn: 139353

removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344

llvm-svn: 139343

MachOObjectFile.cpp:524: error: unused variable 'NumLoadCommands' [-Wunused-variable]

llvm-svn: 139341

llvm-svn: 139339

Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.

llvm-svn: 139330

llvm-svn: 139329

llvm-svn: 139328

llvm-svn: 139325

llvm-svn: 139324

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320

without a base symbol that must not have a relocation entry.

llvm-svn: 139316

Patch by Danil Malyshev!

llvm-svn: 139314

single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.

* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }

* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.

* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.

* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).

Patch by David Meyer

llvm-svn: 139311

in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305

Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304