llvm-svn: 106465

llvm-svn: 106457

llvm-svn: 106455

llvm-svn: 106448

llvm-svn: 106447

llvm-svn: 106446

llvm-svn: 106445

Move part of SSE 1 & 2 compare, shuffle and unpack instructions closely. Preparing them for refactoring and to the addition of their AVX forms

llvm-svn: 106437

Add AVX regular (non-aliased ones) and,or,xor,andn packed instructions. They are already tested in the MC framework, no test needed

llvm-svn: 106436

handling, plus correct R9 handling in that mode.

llvm-svn: 106434

Based on a patch by Patrick Marlier!

llvm-svn: 106433

llvm-svn: 106430

llvm-svn: 106428

This allows the fast regiser allocator to remove redundant 
register moves.
Update a set of tests that depend on the register allocator
to be linear scan. 

llvm-svn: 106420

llvm-svn: 106419

I was trying to do some refactoring on the copyRegToReg, but this is realyl a work in progress and not generally useful yet.

llvm-svn: 106413

used to choke llc with the attached test.
 

llvm-svn: 106411

llvm-svn: 106408

llvm-svn: 106405

llvm-svn: 106399

llvm-svn: 106382

llvm-svn: 106381

llvm-svn: 106375

AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374

llvm-svn: 106373

llvm-svn: 106372

llvm-svn: 106371

llvm-svn: 106370

Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.

llvm-svn: 106368

and operand renaming to help.

The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.

llvm-svn: 106367

llvm-svn: 106366

llvm-svn: 106365

segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364

llvm-svn: 106362

llvm-svn: 106361

llvm-svn: 106360

llvm-svn: 106359

llvm-svn: 106358

llvm-svn: 106357

llvm-svn: 106356