* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.

llvm-svn: 95973

reduce down to a single value.  InstCombine already does this transformation
but DAG legalization may introduce new opportunities.  This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized.  I measured the compile time 
impact of this (running llc on 176.gcc) and it was not significant.

llvm-svn: 95951

This time with fixed test cases.

llvm-svn: 95938

llvm-svn: 95921

Also avoid division by zero.

llvm-svn: 95917

same dead instruction.

llvm-svn: 95890

llvm-svn: 95889

Use SmallVector instead of std::vector for better speed when indirectbr has
few successors.

llvm-svn: 95879

llvm-svn: 95871

llvm-svn: 95840

almost always comments afterwards that need printing.

llvm-svn: 95839

Calling RemoveOperand is very expensive on huge PHI instructions. This makes
early tail duplication run twice as fast on the Firefox JavaScript
interpreter.

llvm-svn: 95832

This makes early tail duplication run 60 times faster when compiling the Firefox
JavaScript interpreter, see PR6186.

llvm-svn: 95831

lowering and requires that certain types exist in ValueTypes.h.  Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements.  It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.

llvm-svn: 95823

llvm-svn: 95819

legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.

llvm-svn: 95816

llvm-svn: 95814

the pointer values could be invalid.

llvm-svn: 95813

changed its behavior.  Oops.

llvm-svn: 95811

different word was intended.

llvm-svn: 95795

llvm-svn: 95781

Now that ShrinkDemandedOps() is separated out from DAG combine. It sometimes leave some obvious nops which dag combine used to clean up afterwards e.g. (trunk (ext n)) -> n. Look for them and squash them.

llvm-svn: 95757

llvm-svn: 95749

llvm-svn: 95748

llvm-svn: 95747

llvm-svn: 95746

llvm-svn: 95745

llvm-svn: 95740

register coalescing.  This fixes many crashes and
places where debug info affects codegen (when
dbg.value is lowered to machine instructions, which
it isn't yet in TOT).

llvm-svn: 95739

The major win of this is that the code is simpler and they 
print on the same line as the instruction again:

        movl    %eax, 96(%esp)          ## 4-byte Spill
        movl    96(%esp), %eax          ## 4-byte Reload
        cmpl    92(%esp), %eax          ## 4-byte Folded Reload
        jl      LBB7_86

llvm-svn: 95738

llvm-svn: 95737

llvm-svn: 95736

the field from being used uninitialized later in some cases.

llvm-svn: 95735

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

llvm-svn: 95730

Only dump output in debug mode.

llvm-svn: 95711

llvm-svn: 95707

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

Patch by M Wahab!

llvm-svn: 95668

llvm-svn: 95647