looking at the size of the pointee. Fixes PR11390!

llvm-svn: 144773

If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges.

llvm-svn: 144772

RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185

llvm-svn: 144771

llvm-svn: 144770

llvm-svn: 144769

llvm-svn: 144768

Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer.

llvm-svn: 144767

llvm-svn: 144759

llvm-svn: 144758

llvm-svn: 144757

llvm-svn: 144756

llvm-svn: 144755

llvm-svn: 144748

llvm-svn: 144747

Fixes PR11375: Different results for 'clang++ huh.cpp'...

llvm-svn: 144746

llvm-svn: 144743

This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

llvm-svn: 144734

failure during bootstrap with it turned on.

llvm-svn: 144731

%arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0
%arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134

Prior to this commit, the GEP instruction that defines %arrayidx136 thought that 
%arrayidx135 was a trivial kill.  The GEP that defines %arrayidx135 doesn't 
generate any code and thus %M0 gets folded into the second GEP.  Thus, we need
to look through GEPs with all zero indices.
rdar://10443319

llvm-svn: 144730

For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727

llvm-svn: 144724

llvm-svn: 144722

llvm-svn: 144721

 

llvm-svn: 144720

llvm-svn: 144719

llvm-svn: 144716

llvm-svn: 144714

llvm-svn: 144713

llvm-svn: 144711

llvm-svn: 144710

llvm-svn: 144709

llvm-svn: 144708

by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

llvm-svn: 144705

'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

llvm-svn: 144701

llvm-svn: 144699

rdar://10435114

llvm-svn: 144698

llvm-svn: 144696

llvm-svn: 144695

rdar://10435076

llvm-svn: 144694

llvm-svn: 144692