gcc 4.4 (due to use of sprintf).

llvm-svn: 60209

being both a namespace and a variable name.

llvm-svn: 60208

llvm-svn: 60188

llvm-svn: 60186

llvm-svn: 60156

llvm-svn: 60145

On x86 favors folding short immediate into some arithmetic operations (e.g. add, and, xor, etc.) because materializing an immediate in a register is expensive in turns of code size.
e.g.
movl 4(%esp), %eax
addl $4, %eax

is 2 bytes shorter than

movl $4, %eax
addl 4(%esp), %eax

llvm-svn: 60139

the conditional for the BRCOND statement. For instance, it will generate:

    addl %eax, %ecx
    jo LOF

instead of

    addl %eax, %ecx
    ; About 10 instructions to compare the signs of LHS, RHS, and sum.
    jl LOF

llvm-svn: 60123

llvm-svn: 60110

Custom lower AND, OR, XOR bitwise operations.

llvm-svn: 60098

llvm-svn: 60095

__attribute__ notation which is supported on more platforms.

llvm-svn: 60083

(a) Remove conditionally removed code in SelectXAddr. Basically, hope for the
    best that the A-form and D-form address predicates catch everything before
    the code decides to emit a X-form address.
(b) Expand vector store test cases to include the usual suspects.

llvm-svn: 60034

they were too tight according to bug 3126.

Fix bug 3126.

llvm-svn: 60006

llvm-svn: 59998

- Mark "add with overflow" as having a custom lowering for X86. Give it a null
  lowering representation for now.

llvm-svn: 59971

(a) Slight rethink on i64 zero/sign/any extend code - use a shuffle to
    directly zero-extend i32 to i64, but use rotates and shifts for
    sign extension. Also ensure unified register consistency.
(b) Add new test harness for i64 operations: i64ops.ll

llvm-svn: 59970

(a) Improve the extract element code: there's no need to do gymnastics with
    rotates into the preferred slot if a shuffle will do the same thing.
(b) Rename a couple of SPUISD pseudo-instructions for readability and better
    semantic correspondence.
(c) Fix i64 sign/any/zero extension lowering.

llvm-svn: 59965

(this doesn't happen that often, since most code
does not use illegal types) then follow it by a
DAG combiner run that is allowed to generate
illegal operations but not illegal types.  I didn't
modify the target combiner code to distinguish like
this between illegal operations and illegal types,
so it will not produce illegal operations as well
as not producing illegal types.

llvm-svn: 59960

llvm-svn: 59958

Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.

llvm-svn: 59953

llvm-svn: 59929

practice these booleans are mostly produced by SetCC,
however the concept is more general.

llvm-svn: 59911

llvm-svn: 59901

ever conceived to occur).

llvm-svn: 59891

llvm-svn: 59872

(a) Fix bgs 3052, 3057
(b) Incorporate Duncan's suggestions re: i1 promotion
(c) Indentation updates.

llvm-svn: 59790

(a) Remove moved file (SPUAsmPrinter.cpp) to make svn happy.
(b) Remove truncated stores that will never be used.
(c) Add initial support for __muldi3 as a libcall.

llvm-svn: 59734

llvm-svn: 59720

promote), fix signed conversion of indexed offsets.

llvm-svn: 59707

llvm-svn: 59703

llvm-svn: 59696

llvm-svn: 59678

llvm-svn: 59677

is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.

This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.

The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.

llvm-svn: 59676

llvm-svn: 59655

right thing and promote the store to i8.

llvm-svn: 59648

Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.

llvm-svn: 59644

llvm-svn: 59637

llvm-svn: 59623