"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414

type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.

llvm-svn: 144373

llvm-svn: 144372

llvm-svn: 144371

llvm-svn: 144370

llvm-svn: 144368

llvm-svn: 144367

VK_Mips_GPOFF_HI/LO.

llvm-svn: 144366

LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.

llvm-svn: 144344

handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253

 - Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250

Patch by Jack Carter.

llvm-svn: 144139

When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100

implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).

Patch by Petar Jovanovic and Sasa Stankovic.

llvm-svn: 144081

llvm-svn: 144019

and add Mips64's version too.

llvm-svn: 144018

registers.

llvm-svn: 144017

floating pointer registers.

llvm-svn: 144016

llvm-svn: 143994

llvm-svn: 143993

is used to save va_arg or byval arguments passed in registers.

llvm-svn: 143992

llvm-svn: 143991

when shift amount is larger than 32.

llvm-svn: 143990

instruction definitions.

llvm-svn: 143989

llvm-svn: 143988

llvm-svn: 143891

added a layer of indirection with no value (not even conciseness).

llvm-svn: 143727

llvm-svn: 143634

llvm-svn: 143218

llvm-svn: 143217

llvm-svn: 143213

The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

llvm-svn: 142930

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

llvm-svn: 142341

llvm-svn: 142332

expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226

llvm-svn: 142220

llvm-svn: 142217

llvm-svn: 142216

llvm-svn: 142214