llvm-svn: 21023

llvm-svn: 21022

Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018

llvm-svn: 21017

llvm-svn: 21016

llvm-svn: 21015

llvm-svn: 21014

llvm-svn: 21013

llvm-svn: 21012

llvm-svn: 21011

llvm-svn: 21010

dont' regen the whole dag if unneccesary.  Second, fix and ugly bug with
the _PARTS nodes that caused legalize to produce multiples of them.
Finally, implement initial support for FABS and FNEG.  Currently FNEG is
the only one to be trusted though.

llvm-svn: 21009

llvm-svn: 21008

llvm-svn: 21007

llvm-svn: 21006

llvm-svn: 21005

llvm-svn: 21004

llvm-svn: 21003

llvm-svn: 21002

llvm-svn: 21001

llvm-svn: 21000

llvm-svn: 20999

llvm-svn: 20996

Generate PowerPC 'subfic' instruction when appropriate

llvm-svn: 20995

llvm-svn: 20994

type support.

llvm-svn: 20993

llvm-svn: 20990

Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.

llvm-svn: 20988

llvm-svn: 20983

llvm-svn: 20982

LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.

llvm-svn: 20981

llvm-svn: 20979

llvm-svn: 20978

part to make sure we get the side effects and to avoid confusing the CFG.

llvm-svn: 20977

llvm-svn: 20976

Fix calls with no arguments

llvm-svn: 20975

18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.

llvm-svn: 20973

llvm-svn: 20972

say that we support them, for the purposes of generating fsel instructions.

llvm-svn: 20970

llvm-svn: 20969