The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

llvm-svn: 105164

Also verify that all subregister indices compose unambiguously.

llvm-svn: 105064

llvm-svn: 104927

llvm-svn: 104912

of the intrinsics.  The goal is to auto-generate both support for GCC-style (vector)
and ARM-style (struct of vector) intrinsics.

This is work in progress, but will be completed soon.

llvm-svn: 104910

llvm-svn: 104874

llvm-svn: 104845

llvm-svn: 104806

llvm-svn: 104755

This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745

llvm-svn: 104741

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704

This reverts commit 104654.

llvm-svn: 104660

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654

llvm-svn: 104650

llvm-svn: 104628

This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615

llvm-svn: 104571

llvm-svn: 104567

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492

llvm-svn: 104452

it.

llvm-svn: 104270

Also rename ABSTRACT to ABSTRACT_STMT

llvm-svn: 104018

llvm-svn: 103760

Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.

llvm-svn: 103746

llvm-svn: 103704

llvm-svn: 103529

llvm-svn: 103457

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

doesn't have to guess.

llvm-svn: 103194

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

llvm-svn: 103164

when building llvm with clang

llvm-svn: 103084

llvm-svn: 103073

llvm-svn: 103071

and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.

llvm-svn: 103050

name (for example, to allow targets to interpose the actual MatchInstruction
function).

llvm-svn: 102987

sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026

llvm-svn: 102815

memory operands rather than immediate operands.

llvm-svn: 102217