Partial fix for rdar://9945172.

llvm-svn: 137513

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.

llvm-svn: 137502

llvm-svn: 137499

Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.

llvm-svn: 137494

llvm-svn: 137487

integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484

llvm-svn: 137481

llvm-svn: 137476

when building with assertions disabled.

llvm-svn: 137460

Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.

llvm-svn: 137404

llvm-svn: 137389

warning. 

llvm-svn: 137378

llvm-svn: 137375

llvm-svn: 137372

llvm-svn: 137371

llvm-svn: 137370

llvm-svn: 137368

llvm-svn: 137367

llvm-svn: 137364

llvm-svn: 137363

inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362

llvm-svn: 137359

llvm-svn: 137356

llvm-svn: 137353

llvm-svn: 137351

llvm-svn: 137347

llvm-svn: 137345

llvm-svn: 137344

llvm-svn: 137342

llvm-svn: 137340

llvm-svn: 137339

llvm-svn: 137337

llvm-svn: 137331

llvm-svn: 137325

llvm-svn: 137324

llvm-svn: 137323

Correct immediate range for shifter operands.  Patch by James Molloy, with additional encoding fixes added by me.

llvm-svn: 137322

llvm-svn: 137320

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318

Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316