llvm-svn: 146702

Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value.  (This is just to be safe; I don't think this actually causes any issues in practice.)

llvm-svn: 146700

llvm-svn: 146699

[asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports.

llvm-svn: 146698

llvm-svn: 146692

llvm-svn: 146691

The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689

[asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.

llvm-svn: 146688

llvm-svn: 146686

llvm-svn: 146685

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684

llvm-svn: 146682

llvm-svn: 146678

llvm-svn: 146675

llvm-svn: 146674

Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.

llvm-svn: 146671

Patch by Kyriakos Georgiou!

llvm-svn: 146670

llvm-svn: 146666

llvm-svn: 146665

llvm-svn: 146664

The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

llvm-svn: 146657

Patch by Kyriakos Georgiou.

llvm-svn: 146656

llvm-svn: 146642

llvm-svn: 146639

Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.

llvm-svn: 146630

llvm-svn: 146627

rdar://10566486

llvm-svn: 146625

These can be reduced to "~cond & x" or "~cond | x"

llvm-svn: 146624

Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls.  These are already marked as illegal by default.

llvm-svn: 146623

Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header).  Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads.  PR11575.

llvm-svn: 146621

Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order.

llvm-svn: 146617

buffer copy.  Suggestion by Chris Lattner!

llvm-svn: 146614

the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.

llvm-svn: 146612

into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.

llvm-svn: 146610

An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

llvm-svn: 146609

llvm-svn: 146608

llvm-svn: 146605

On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.

llvm-svn: 146604

llvm-svn: 146603