don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529

llvm-svn: 40132

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 36834

clobbered by a call.

llvm-svn: 36448

llvm-svn: 36359

llvm-svn: 36355

X86 32 bits.

llvm-svn: 36283

Also, fixed static case in presence of eax livin. This fixes PR331

PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195

llvm-svn: 35869

llvm-svn: 35230

llvm-svn: 33537

llvm-svn: 33486

- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.

llvm-svn: 32238

- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.

llvm-svn: 32046

llvm-svn: 32017

llvm-svn: 31435

generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.

llvm-svn: 31299

llvm-svn: 30945

llvm-svn: 30907

that it can't assume ESP is unmodified across the instrs.

llvm-svn: 30905

llvm-svn: 30891

llvm-svn: 30844

llvm-svn: 30583

operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241

llvm-svn: 30177

using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.

llvm-svn: 30156

llvm-svn: 30152

llvm-svn: 29603

llvm-svn: 29228

llvm-svn: 29194

llvm-svn: 29110

llvm-svn: 28980

llvm-svn: 28938

vector types are passed via XMM registers.

llvm-svn: 28789

llvm-svn: 28666

llvm-svn: 28606