llvm-svn: 31654

by the shr -> [al]shr patch.  This was reduced from 176.gcc.

llvm-svn: 31653

llvm-svn: 31652

llvm-svn: 31650

llvm-svn: 31649

take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.

This fixes PR996.

llvm-svn: 31645

CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast

llvm-svn: 31644

llvm-svn: 31643

Inherit CommonPassManagerImpl from Pass.

llvm-svn: 31642

SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.

llvm-svn: 31641

llvm-svn: 31639

llvm-svn: 31638

llvm-svn: 31637

llvm-svn: 31636

llvm-svn: 31635

llvm-svn: 31634

llvm-svn: 31633

llvm-svn: 31632

When forming a pre-indexed store, make sure ptr isn't the same or is a pred of value being stored. It would cause a cycle.

llvm-svn: 31631

llvm-svn: 31630

llvm-svn: 31629

llvm-svn: 31627

(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)

This is disabled unless -enable-ppc-preinc is passed to llc for now.

llvm-svn: 31621

llvm-svn: 31619

have to be a subpart of a complex operand.

llvm-svn: 31618

llvm-svn: 31617

Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.

llvm-svn: 31616

This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).

llvm-svn: 31613

llvm-svn: 31612

llvm-svn: 31610

llvm-svn: 31609

llvm-svn: 31608

llvm-svn: 31607

llvm-svn: 31606

llvm-svn: 31605

llvm-svn: 31604

llvm-svn: 31603

lazy compilation is ever attempted

llvm-svn: 31602

llvm-svn: 31601

llvm-svn: 31600