a register to 0. This fixes PR4814.

llvm-svn: 80445

  encodings.
- Make some of the values emitted by the FDEs dependent upon the pointer
  size. This is in line with how GCC does things. And it has the benefit of
  working for Darwin in 64-bit mode now.

llvm-svn: 80428

llvm-svn: 80409

llvm-svn: 80408

Use MDNodes to encode debug info in llvm IR.

llvm-svn: 80406

Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.

llvm-svn: 80404

Some other minor win64 fixes as well.

Patch by Michael Beck!

llvm-svn: 80370

llvm-svn: 80354

llvm-svn: 80350

llvm-svn: 80338

llvm-svn: 80322

llvm-svn: 80280

Add MO flags to simplify the printing of relocations.
Remove the support for printing large code model relocs (which
aren't supported anyway).

llvm-svn: 80278

llvm-svn: 80271

llvm-svn: 80269

llvm-svn: 80268

scalar_to_vector is fully legal now

llvm-svn: 80251

llvm-svn: 80250

No idea whether this is profitable or not.

llvm-svn: 80245

See http://llvm.org/PR4687 for more info and links.

llvm-svn: 80244

 - Note, this is a gigantic hack, with the sole purpose of unblocking further
   work on the assembler (its also possible to test the mathcer more completely
   now).

 - Despite being a hack, its actually good enough to work over all of 403.gcc
   (although some encodings are probably incorrect). This is a testament to the 
   beauty of X86's MachineInstr, no doubt! ;)

llvm-svn: 80234

llvm-svn: 80232

Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.

llvm-svn: 80191

llvm-svn: 80186

moves. This avoids the need to promote the operands (or implicitly
extend them, a partial register update condition), and can reduce
i8 register pressure. This substantially speeds up code such as
write_hex in lib/Support/raw_ostream.cpp.

subclass-coalesce.ll is too trivial and no longer tests what it was
originally intended to test.

llvm-svn: 80184

llvm-svn: 80176

llvm-svn: 80124

llvm-svn: 80121

llvm-svn: 80119

The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117

llvm-svn: 80115

llvm-svn: 80107

backends don't use it as an example.

llvm-svn: 80105

leads to partial-register definitions. To help avoid redundant
zero-extensions, also teach the h-register matching patterns that
use movzbl to match anyext as well as zext.

llvm-svn: 80099

llvm-svn: 80085

llvm-svn: 80073

llvm-svn: 80070

code hints that it would be a good idea to inline
a function ("inline" keyword).  No functional change
yet; FEs do not emit this and inliner does not use it.

llvm-svn: 80063

llvm-svn: 80042

PIC16Section will move to MCSectionPIC16.

llvm-svn: 80021