llvm-svn: 123585

into and/shift would cause nodes to move around and a dangling pointer
to happen.  The code tried to avoid this with a HandleSDNode, but 
got the details wrong.

llvm-svn: 123578

llvm-svn: 123572

llvm-svn: 123567

llvm-svn: 123561

llvm-svn: 123560

multi-instruction sequences like calls.  Many thanks to Jakob for
finding a testcase.

llvm-svn: 123559

llvm-svn: 123556

llvm-svn: 123505

llvm-svn: 123497

llvm-svn: 123494

declaration and its assignments.

Found by clang static analyzer.

llvm-svn: 123486

Add a possibility to switch between CFI directives- and table-based frame description emission. Currently all the backends use table-based stuff.

llvm-svn: 123476

llvm-svn: 123475

llvm-gcc-i386-linux-selfhost buildbot heartburn...

llvm-svn: 123431

llvm-svn: 123427

- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424

llvm-svn: 123422

after sext's generated for addressing that got folded.  Previously we compiled
test5 into:

_test5:                                 ## @test5
## BB#0:
        movq    -8(%rsp), %rax          ## 8-byte Reload
        movq    (%rdi,%rax), %rdi
        addq    %rdx, %rdi
        movslq  %esi, %rax
        movq    %rax, -8(%rsp)          ## 8-byte Spill
        movq    %rdi, %rax
        ret

which is insane and wrong.  Now we produce:

_test5:                                 ## @test5
## BB#0:
	movslq	%esi, %rax
	movq	(%rdi,%rax), %rax
	addq	%rdx, %rax
	ret

llvm-svn: 123414

Fixes <rdar://problem/8857982>.

llvm-svn: 123409

llvm-svn: 123408

llvm-svn: 123406

llvm-svn: 123405

the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, #0, r3, c13, c0, #3

Fixes <rdar://problem/8857858>.

llvm-svn: 123404

llvm-svn: 123399

llvm-svn: 123397

directional local labels like 1f and 2b.

llvm-svn: 123393

set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

llvm-svn: 123387

in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369

16 bytes for PR8969. Update all testcases accordingly.

llvm-svn: 123367

.code 32 if the TargetMachine's isThumb() boolean does not match.  The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.

llvm-svn: 123353

llvm-svn: 123350

llvm-svn: 123341

that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340

enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321

of the switch block to appease GCC.

llvm-svn: 123317

llvm-svn: 123315

llvm-svn: 123310

ensure %o7 is not assigned as the destination of getpcx instruction.

llvm-svn: 123304

are correctly marked as used instead of passing all possible argument registers
as used.  

llvm-svn: 123301