llvm-svn: 25981

llvm-svn: 25980

This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.

llvm-svn: 25979

llvm-svn: 25978

llvm-svn: 25976

llvm-svn: 25975

#LLVM LOC, and auto-cse's cast instructions.

llvm-svn: 25974

llvm-svn: 25973

tblgen patch reverted.

llvm-svn: 25971

llvm-svn: 25969

Select them afterwards if it returns true.

llvm-svn: 25968

case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.

llvm-svn: 25967

llvm-svn: 25966

llvm-svn: 25965

1. When rewriting code in outer loops, sometimes we would insert code into
   inner loops that is invariant in that loop.
2. Notice that 4*(2+x) is 8+4*x and use that to simplify expressions.

This is a performance neutral change.

llvm-svn: 25964

llvm-svn: 25963

llvm-svn: 25962

1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
   ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
   up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.

llvm-svn: 25961

llvm-svn: 25960

llvm-svn: 25958

llvm-svn: 25957

int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr

llvm-svn: 25955

llvm-svn: 25954

flag so it can be flagged to a FST.

llvm-svn: 25953

llvm-svn: 25952

llvm-svn: 25951

llvm-svn: 25949

store EAX -> [ss#0]
[ss#0] += 1
...
use(EAX)

In this case, it is not valid to rewrite this as:


store EAX -> [ss#0]
EAX += 1
store EAX -> [ss#0]  ;;; this would also delete the store above
...
use(EAX)

... because EAX is not a dead at that point.  Keep track of which registers
we are allowed to clobber, and which ones we aren't, and don't clobber the
ones we're not supposed to.  :)

This should resolve the issues on X86 last night.

llvm-svn: 25948

and PhysRegsAvailable maps out into a new AvailableSpills struct.  No
functionality change.

This paves the way for a bugfix, coming up next.

llvm-svn: 25947

llvm-svn: 25946

llvm-svn: 25945

llvm-svn: 25944

llvm-svn: 25943

llvm-svn: 25942

llvm-svn: 25941

llvm-svn: 25940

obsolete.  yaay :)

llvm-svn: 25939

instruction when possible.

llvm-svn: 25938

Remove the dead getRegClassForType method
minor formating changes.

llvm-svn: 25936

llvm-svn: 25935