llvm-svn: 118193

llvm-svn: 118192

llvm-svn: 118190

llvm-svn: 118187

all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183

on non-X86 hosts.  Hopefully fixes ppc-host buildbot.

llvm-svn: 118182

llvm-svn: 118176

For NEON we had been assuming this was always an immediate constant.

llvm-svn: 118175

Makes it more clear that it is just a path manipulation function.

llvm-svn: 118174

llvm-svn: 118173

the code more self-documenting.

llvm-svn: 118171

with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169

llvm-svn: 118168

value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167

this by using an undef as a pointer.

Fixes rdar://8625016

llvm-svn: 118164

llvm-svn: 118163

Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.

llvm-svn: 118160

llvm-svn: 118152

llvm-svn: 118151

easier to read.

llvm-svn: 118148

    vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144

encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.

llvm-svn: 118143

llvm-svn: 118141

printOperand() asm printer helper functions. rdar://8425198

llvm-svn: 118140

llvm-svn: 118139

parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135

latencies) of loads.

llvm-svn: 118134

llvm-svn: 118133

llvm-svn: 118131

llvm-svn: 118130

llvm-svn: 118128

llvm-svn: 118127

llvm-svn: 118126

instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125

llvm-svn: 118124

llvm-svn: 118122

llvm-svn: 118121

llvm-svn: 118120

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119