Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins.

llvm-svn: 117506

the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505

small tweaks to reflect statements of what really ever shipped.  ABI is, and has been, accurate for what we ship.

llvm-svn: 117504

llvm-svn: 117503

llvm-svn: 117502

for specifying fractional bits for fixed point conversions.

llvm-svn: 117501

type-based visibility.

llvm-svn: 117500

not loading the specializations of a class template until some AST
consumer needs them.

llvm-svn: 117498

llvm-svn: 117497

llvm-svn: 117496

llvm-svn: 117495

llvm-svn: 117494

disabled.

llvm-svn: 117493

reconcile missing typos & delete obsolete pre-SnowLeopard section w.r.t. prior repository for this document

llvm-svn: 117492

aggressive about the form we expect bools to be in.  I don't really have
time to fix all the sources right now.

llvm-svn: 117486

llvm-svn: 117485

// rdar: // 8600553.

llvm-svn: 117484

llvm-svn: 117483

elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482

llvm-svn: 117481

some excessive recursion and deserialization.

llvm-svn: 117480

statement-expression. // rdar: //8600553

llvm-svn: 117479

llvm-svn: 117478

llvm-svn: 117477

eliminate some excessive recursion and deserialization.

llvm-svn: 117476

llvm-svn: 117475

llvm-svn: 117474

There are currently 100 references to COFF::IMAGE_SCN in 6 files
and 11 different functions. Section to attribute mapping really
needs to happen in one place to avoid problems like this.

llvm-svn: 117473

llvm-svn: 117472

llvm-svn: 117471

sure they come out at the correct times.

llvm-svn: 117470

llvm-svn: 117469

llvm-svn: 117468

llvm-svn: 117466

llvm-svn: 117463

llvm-svn: 117462

operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461

llvm-svn: 117460

llvm-svn: 117459

llvm-svn: 117458