llvm-svn: 5220

* Convert to use PHIElimination pass
* Don't spill values which have just been reloaded (big win reducing spills)
* Add experimental support for eliminating spills before TwoAddress
  instructions.  It currently is broken so it is #ifdef'd out.
* Use new "is terminator" flag on instructions instead of looking for
  branches and returns explicitly.

llvm-svn: 5219

llvm-svn: 5218

llvm-svn: 5217

Add helper methods for MachineFrameInfo

llvm-svn: 5216

llvm-svn: 5215

llvm-svn: 5214

* Add new M_TERMINATOR_FLAG

llvm-svn: 5213

llvm-svn: 5212

llvm-svn: 5211

llvm-svn: 5210

* Add new isPCRelative modifier flag which should be used in place of MO_PCRelativeDisp type.
* Fix a bug in isPhysicalRegister
* Add new setOpcode and RemoveOperand methods

llvm-svn: 5209

llvm-svn: 5208

llvm-svn: 5207

* Add support for functions referenced by name

llvm-svn: 5206

llvm-svn: 5205

llvm-svn: 5204

Rename MachineCacheInfo to TargetCacheInfo

llvm-svn: 5203

Rename MachineOptInfo to TargetoptInfo
Rename MachineCacheInfo to TargetCacheInfo

llvm-svn: 5202

llvm-svn: 5201

llvm-svn: 5200

llvm-svn: 5199

of the abstract frame representation

llvm-svn: 5198

llvm-svn: 5197

* Use new FunctionFrameInfo object to manage stack slots instead of doing
  it directly
* Adjust to new MRegisterInfo API
* Don't take a TM as a ctor argument
* Don't keep track of which callee saved registers are modified
* Don't emit prolog/epilog code or spill/restore code for callee saved regs
* Use new allocation_order_begin/end iterators to simplify dramatically the
  logic for picking registers to allocate
* Machine PHI nodes can no longer contain constant arguments

* Use a bitvector to keep track of registers used instead of a set
* Fix problem where explicitly referenced registers would be added to
  regsused set and never removed

llvm-svn: 5196

* Use new FunctionFrameInfo object to manage stack slots instead of doing
  it directly
* Adjust to new MRegisterInfo API
* Don't take a TM as a ctor argument
* Don't keep track of which callee saved registers are modified
* Don't emit prolog/epilog code or spill/restore code for callee saved regs
* Use new allocation_order_begin/end iterators to simplify dramatically the
  logic for picking registers to allocate
* Machine PHI nodes can no longer contain constant arguments

llvm-svn: 5195

llvm-svn: 5194

  into a new MachineFunctionInfo class
* Implement new FunctionFrameInfo class

llvm-svn: 5193

llvm-svn: 5192

llvm-svn: 5191

llvm-svn: 5190

llvm-svn: 5189

* most pass ctors no longer take TM arguments
* New prolog/epilog insertion pass

llvm-svn: 5188

llvm-svn: 5187

* Include contents of X86RegisterClasses.cpp into here
* Adjustments to register api to work with new frame manager
* Eliminate moveImm2Reg, getFramePointer, and getStackPointer
* Cleanup and simplify prolog/epilog code generation
* Prolog/epilog are MUCH more efficient now.

llvm-svn: 5186

llvm-svn: 5185

llvm-svn: 5184

* Remove some size suffixes [bwl]
* Add new ADJCALLSTACKDOWN & ADJCALLSTACKUP pseudo instrs
* Call instructions are M_CALL not M_BRANCH!
* Disable push and pop instructions
* Add new ANDri32 instr

llvm-svn: 5183

llvm-svn: 5182

* New createPrologEpilogCodeInserter() function

llvm-svn: 5181