llvm-svn: 116072

llvm-svn: 116069

llvm-svn: 116068

''const'ify getMachineOpValue() and associated helpers.'

llvm-svn: 116067

llvm-svn: 116064

llvm-svn: 116063

llvm-svn: 116061

llvm-svn: 116059

Start separating out code metrics into code size metrics and code performance metrics.  Partial Specialization will apply the former to function specializations, and the latter to all callsites that can use a specialization, in order to decide whether to create a specialization

llvm-svn: 116057

Small patch to restore home register stack space allocation for the Win64 case.  Add test case.  This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.

llvm-svn: 116056

callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.

llvm-svn: 116055

llvm-svn: 116054

the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.

llvm-svn: 116053

llvm-svn: 116052

llvm-svn: 116051

llvm-svn: 116050

reapply: reimplement the second half of the or/add optimization.  We should now

with no changes.  Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.

llvm-svn: 116040

"Reimplement (part of) the or -> add optimization.  Matching 'or' into 'add'"

With a critical fix: the add pseudos clobber EFLAGS.

llvm-svn: 116039

llvm-svn: 116038

llvm-svn: 116037

llvm-svn: 116036

llvm-svn: 116034

'add'", which seems to have broken just about everything.

llvm-svn: 116033

on r116007, which I am about to revert.

llvm-svn: 116032

which depends on r116007, which I am about to revert.

llvm-svn: 116031

llvm-svn: 116030

as thumb1.

Fixes lencod.

llvm-svn: 116027

only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".

llvm-svn: 116026

llvm-svn: 116024

llvm-svn: 116022

llvm-svn: 116021

llvm-svn: 116018

casing FsMOVAPDrr/FsMOVAPSrr.

llvm-svn: 116016

llvm-svn: 116015

llvm-svn: 116014

llvm-svn: 116013

one user. This code will be restructured soon and FormulaSorter
is getting in the way.

llvm-svn: 116012

llvm-svn: 116011

not just base registers.

llvm-svn: 116010

llvm-svn: 116009