all over the place in different styles and variants.  Standardize on two
preferred entrypoints: one that takes a StructType and ArrayRef, and one that
takes StructType and varargs.

In cases where there isn't a struct type convenient, we now add a
ConstantStruct::getAnon method (whose name will make more sense after a few
more patches land).  

It would be "really really nice" if the ConstantStruct::get and 
ConstantVector::get methods didn't make temporary std::vectors.

llvm-svn: 133412

equality check.

llvm-svn: 133409

A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.

The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.

For example, the ARM QQ register class of pseudo-registers could have
been formed like this:

  // Form pairs Q0_Q1, Q2_Q3, ...
  def QQPairs : RegisterTuples<[qsub_0, qsub_1],
                               [(decimate QPR, 2),
                                (decimate (shl QPR, 1), 2)]>;

  def QQ : RegisterClass<..., (add QQPairs)>;

Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:

  // Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
  def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
                                   [(rotl DPR, 0),
                                    (rotl DPR, 1),
                                    (rotl DPR, 2)]>;

TableGen automatically computes aliasing information for the synthesized
registers.

Register tuples are still somewhat experimental. We still need to see
how they interact with MC.

llvm-svn: 133407

const Constant *.

llvm-svn: 133400

llvm-svn: 133390

llvm-svn: 133389

llvm-svn: 133388

instead of scalarizing, and doing an element-by-element truncat.

llvm-svn: 133382

llvm-svn: 133381

expressions, but Chris wants to instead reduce the set of possible constant
expression types.

llvm-svn: 133374

can manipulate instructions and constantexpr's uniformly. No users yet though.

llvm-svn: 133373

top level type without a specified number.  This syntax isn't documented
and blocks forward progress.

llvm-svn: 133371

llvm-svn: 133369

top level type without a specified number.  This asmprinter has never
generated this, as you can tell by no tests being updated.  It also isn't
documented.

llvm-svn: 133368

much cleaner.

llvm-svn: 133364

llvm-svn: 133363

llvm-svn: 133362

now that Type::getDescription() is dead, the TypePrinting class can move from Assembly/Writer.h to being 
a private class in AsmWriter.cpp.

llvm-svn: 133361

removes some gunk from LLVMContext.

llvm-svn: 133360

llvm-svn: 133359

llvm-svn: 133356

temporary std::string for every function being checked.

llvm-svn: 133355

llvm-svn: 133352

llvm-svn: 133351

llvm-svn: 133350

llvm-svn: 133349

llvm-svn: 133348

llvm-svn: 133347

In cases such as the attached test, where the case value for a switch
destination is used in a phi node that follows the destination, it
might be better to replace that value with the condition value of the
switch, so that more blocks can be folded away with
TryToSimplifyUncondBranchFromEmptyBlock because there are less
conflicts in the phi node.

llvm-svn: 133344

llvm-svn: 133339

type's bitwidth matches the (allocated) size of the alloca. This severely
pessimizes vector scalar replacement when the only vector type being used is
something like <3 x float> on x86 or ARM whose allocated size matches a
<4 x float>.

I hope to fix some of the flawed assumptions about allocated size throughout
scalar replacement and reenable this in most cases.

llvm-svn: 133338

for pre-2.9 bitcode files.  We keep x86 unaligned loads, movnt, crc32, and the
target indep prefetch change.

As usual, updating the testsuite is a PITA.

llvm-svn: 133337

alloca. Fixes part of <rdar://problem/9580800>.

llvm-svn: 133336

unless ScalarKind is Vector.

llvm-svn: 133335

This should fix the Linux buildbots.

llvm-svn: 133334

Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

llvm-svn: 133333

Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

llvm-svn: 133332

llvm-svn: 133331

This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:

Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After:  %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
llvm-svn: 133326

llvm-svn: 133325