ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094

llvm-svn: 118093

llvm-svn: 118029

llvm-svn: 117997

llvm-svn: 117984

This is another part of the fix for Radar 8599955.

llvm-svn: 117976

llvm-svn: 117929

got a dulicated line).

llvm-svn: 117860

llvm-svn: 117859

Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858

There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756

llvm-svn: 117753

encoder functions.

llvm-svn: 117738

the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714

llvm-svn: 117703

llvm-svn: 117702

llvm-svn: 117695

llvm-svn: 117687

vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626

llvm-svn: 117571

llvm-svn: 117531

llvm-svn: 117520

- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519

complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509

the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505

for specifying fractional bits for fixed point conversions.

llvm-svn: 117501

llvm-svn: 117478

rdar://8477752.

llvm-svn: 117419

llvm-svn: 117418

explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409

llvm-svn: 117188

llvm-svn: 117165

llvm-svn: 117133

llvm-svn: 117121

definitions.

llvm-svn: 117114

llvm-svn: 117108

llvm-svn: 117080

llvm-svn: 117076

llvm-svn: 117072