llvm-svn: 144784

The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

llvm-svn: 144781

llvm-svn: 144777

llvm-svn: 144743

This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

llvm-svn: 144734

For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727

llvm-svn: 144722

 

llvm-svn: 144720

llvm-svn: 144713

llvm-svn: 144710

llvm-svn: 144709

by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

llvm-svn: 144705

'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

llvm-svn: 144701

rdar://10435114

llvm-svn: 144698

llvm-svn: 144695

rdar://10435076

llvm-svn: 144694

llvm-svn: 144692

Yet more of rdar://10435076.

llvm-svn: 144691

rdar://10449856.

llvm-svn: 144689

Ongoing rdar://10435114.

llvm-svn: 144688

rdar://10449724

llvm-svn: 144684

llvm-svn: 144683

When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679

registers and instructions when ABI is N64.

llvm-svn: 144666

register.

llvm-svn: 144665

llvm-svn: 144664

llvm-svn: 144655

llvm-svn: 144654

rdar://10435076

llvm-svn: 144650

llvm-svn: 144633

of PseudoSourceValue from lib/Target/.

llvm-svn: 144632

llvm-svn: 144631

Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.

llvm-svn: 144629

Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.

llvm-svn: 144622

integer variants. rdar://10437054

llvm-svn: 144608

rdar://10435076

llvm-svn: 144606

Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

llvm-svn: 144602

rdar://10435076

llvm-svn: 144593

rdar://10435076

llvm-svn: 144592

llvm-svn: 144589