llvm-svn: 194569

This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.

llvm-svn: 194562

The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

llvm-svn: 194512

copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501

llvm-svn: 194416

llvm-svn: 194394

On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

llvm-svn: 194285

[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)

llvm-svn: 194263

llvm-svn: 194262

llvm-svn: 194261

llvm-svn: 194258

The encoding was updated in MSA r1.07.

llvm-svn: 194255

[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings

llvm-svn: 194253

llvm-svn: 194205

Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.

llvm-svn: 194145

llvm-svn: 194123

llvm-svn: 194118

Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

llvm-svn: 194094

llvm-svn: 194085

Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043

llvm-svn: 193992

llvm-svn: 193816

llvm-svn: 193798

llvm-svn: 193790

This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739

currently supported in the ELF object writer, along with a simple test case.

llvm-svn: 193709

llvm-svn: 193705

llvm-svn: 193691

llvm-svn: 193623

Add some missing tests, factor out a test not specific to v8 into
its own file.

llvm-svn: 193611

Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.

Differential Revision: http://llvm-reviews.chandlerc.com/D2036

llvm-svn: 193599

ELF. They can overlap with the other symbols, e.g. if a source file
"foo.c" contains a function "foo" with a static variable "c".

llvm-svn: 193569

llvm-svn: 193548

llvm-svn: 193547

llvm-svn: 193546

llvm-svn: 193539

llvm-svn: 193538

llvm-svn: 193537

llvm-svn: 193536

an MCExpr, in order to avoid writing an encoded zero value in the immediate
field.

When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we
don't know what the final immediate field value should be. We shouldn't
explicitly set the immediate field to an encoded zero value as zero is encoded
with a non-zero bit pattern. This leads to bits being set that pollute the
final immediate value. The nature of the encoding is such that the polluted
bits only affect very large immediate values, explaining why this hasn't
caused problems earlier.

Fixes <rdar://problem/15155975>.

llvm-svn: 193535