clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.

llvm-svn: 146168

Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp

  if (HasAVX)
    X86SSELevel = NoMMXSSE;

This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.

The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.

However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297

llvm-svn: 146163

sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.

llvm-svn: 146157

llvm-svn: 146151

We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.

llvm-svn: 146150

Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).

llvm-svn: 146143

MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)

llvm-svn: 146137

llvm-svn: 146136

llvm-svn: 146125

It is not used any more. We are tracking inline assembly misalignments
directly through the BBInfo.Unalign and KnownBits fields.

A simple conservative size estimate is not good enough since it can
cause alignment padding to be underestimated.

llvm-svn: 146124

llvm-svn: 146123

llvm-svn: 146121

llvm-svn: 146120

llvm-svn: 146119

Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

llvm-svn: 146118

llvm-svn: 146116

llvm-svn: 146115

llvm-svn: 146114

Simplify code.

llvm-svn: 146112

llvm-svn: 146111

llvm-svn: 146109

ExceptionDemo example.

llvm-svn: 146108

llvm-svn: 146107

For 'gas' compatibility.

llvm-svn: 146106

RDHWR. 

llvm-svn: 146101

llvm-svn: 146100

llvm-svn: 146099

llvm-svn: 146097

llvm-svn: 146096

llvm-svn: 146095

llvm-svn: 146093

llvm-svn: 146091

Nothing too interesting at this point, but comments are welcome.
Part of rdar://9860654 and PR5680.

llvm-svn: 146090

been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

llvm-svn: 146088

Make sure we correctly set LiveRegGens when a call is unscheduled.  <rdar://problem/10460321>.  No testcase because this is very sensitive to scheduling.

llvm-svn: 146087

llvm-svn: 146086

llvm-svn: 146083

llvm-svn: 146081

llvm-svn: 146080

files.  First, add a new block USELIST_BLOCK to the bitcode format.  This is 
where USELIST_CODE_ENTRYs will be stored.  The format of the USELIST_CODE_ENTRYs
have not yet been defined.  Add support in the BitcodeReader for parsing the
USELIST_BLOCK.
Part of rdar://9860654 and PR5680.

llvm-svn: 146078