- This is "extraordinarily" Darwin 'as' compatible. See the litany of FIXMEs littered about for more information.
 - There are a few cases which seem to clearly be 'as' bugs which I have left unsupported, and there is one cases where we diverge but should fix if it blocks diffing .o files (Darwin 'as' ends up widening a jump unnecessarily).
 - 403.gcc build, runs, and diffs equivalently to the 'as' built version now (using llvm-mc). However, it builds so slowly that I wouldn't recommend trying it quite yet. :)

llvm-svn: 98974

MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.

llvm-svn: 98972

room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

llvm-svn: 98967

back out r98957, it broke http://smooshlab.apple.com:8010/builders/clang-x86_64-darwin10-fnt/builds/703 in the nightly test suite

llvm-svn: 98958

This time I did a self-hosted bootstrap on Linux x86-64,
with no problems. Let's see how darwin 64-bit self-hosting
goes. At the first sign of failure I'll back this out.

Maybe the valgrind bots give me a hint of what may be wrong
(it at all).

llvm-svn: 98957

 - MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.

llvm-svn: 98955

llvm-svn: 98954

llvm-svn: 98953

llvm-svn: 98952

llvm-svn: 98950

llvm-svn: 98949

llvm-svn: 98948

MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task.

llvm-svn: 98947

MC/Mach-O: Lift the fixup evaluation and application up (to the same place), and eliminate MCAsmFixup::FixedValue.

llvm-svn: 98944

MC/Mach-O: Factor out ExecutePostLayoutBinding, to separate the post-layout changes the object writer may need to make to the assembler from the actual .o writing.

llvm-svn: 98943

MC/Mach-O: Lift relocation emission logic a bit higher to separate evaluation / relocation handling from the actual .o writing.

llvm-svn: 98942

llvm-svn: 98941

createAsmStreamer now takes ownership of the instprinter.

llvm-svn: 98939

need them.

llvm-svn: 98937

llvm-svn: 98936

dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934

llvm-svn: 98932

match.  Jakob, please take a look when you get a chance.

llvm-svn: 98931

can't match or just have no testcases.  Will remove after 
confirmation from dan that they really are dead.

llvm-svn: 98930

llvm-svn: 98928

MC/Mach-O: Add isScatteredFixupFullyResolved, which implements the correct algorithm (used on x86_64) for determining whether an evaluated fixup is fully resolved (doesn't need relocation).
 - Test cases will follow, once we have x86_64 relocation support.

llvm-svn: 98926

 - These find the defining symbol which identifies the containing atom for a symbol or address. They are currently very slow, but will be eliminated eventually.

llvm-svn: 98925

llvm-svn: 98924

MC/Mach-O: Factor out isSymbolLinkerVisible method; "linker visible" is a made up term to refer to non-temporary labels + temporary labels in sections-which-require symbols. For Darwin, it corresponds to symbols which effectively define an atom.

llvm-svn: 98923

llvm-svn: 98920

llvm-svn: 98919

llvm-svn: 98911

to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903

llvm-svn: 98902

llvm-svn: 98901

llvm-svn: 98889

llvm-svn: 98888

Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.

llvm-svn: 98887

llvm-svn: 98881

were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880