llvm-svn: 152136

llvm-svn: 152135

 - On OS X 10.7+ this is apparently recommended practice. This maybe should
   become a configurey thing one day, but I'm not sure it is right to
   automatically turn it on.

llvm-svn: 152133

llvm-svn: 152131

llvm-svn: 152129

llvm-svn: 152127

llvm-svn: 152122

Fixes 1242 warnings from gcc during clang build.

llvm-svn: 152120

implementation. Patch by Meador Inge

llvm-svn: 152116

llvm-svn: 152115

llvm-svn: 152114

llvm-svn: 152113

llvm-svn: 152112

llvm-svn: 152111

llvm-svn: 152110

llvm-svn: 152107

use the first pointer type for it. Rename it to getAddrOfPtr1().

llvm-svn: 152106

Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that.

llvm-svn: 152105

llvm-svn: 152104

Increase number of allowed registers in register classes to 64k instead of 256. Widen register class ID to 16-bits. Widen register size and alignment to be up to 64k bytes instead of 256 bytes. This partially reverts r152019 to be less restrictive.

llvm-svn: 152100

llvm-svn: 152099

It is just a worse version of TinyPtrVector.

llvm-svn: 152097

When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

llvm-svn: 152095

llvm-svn: 152094

Based on a writeup originally by Greg Clayton.

Abuse div and pre tags horribly. Needs a bit more cleanup.

llvm-svn: 152093

llvm-svn: 152092

optimizes the case where there is only one element.

llvm-svn: 152090

llvm-svn: 152089

Make it possible for a target to mark FSUB as Expand.  This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.

llvm-svn: 152079

The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076

llvm-svn: 152070

rdar://10988114

llvm-svn: 152068

llvm-svn: 152067

llvm-svn: 152066

Use the new composite physical registers.

llvm-svn: 152063

llvm-svn: 152061

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045

llvm-svn: 152044

Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043

Patch by Sean Silva!

llvm-svn: 152042