is not found.

llvm-svn: 37164

cause other regressions.

llvm-svn: 37160

llvm-svn: 37159

llvm-svn: 37158

of verifying result values when debugging.

llvm-svn: 37156

llvm-svn: 37154

undefined behavior when the width > 64 bits.

llvm-svn: 37153

llvm-svn: 37151

llvm-svn: 37141

llvm-svn: 37140

llvm-svn: 37139

llvm-svn: 37138

llvm-svn: 37134

llvm-svn: 37131

llvm-svn: 37130

llvm-svn: 37126

llvm-svn: 37125

llvm-svn: 37124

llvm-svn: 37123

llvm-svn: 37121

llvm-svn: 37120

llvm-svn: 37119

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118

llvm-svn: 37117

Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.

llvm-svn: 37116

Rename M_PREDICATED to M_PREDICABLE; Move TargetInstrInfo::isPredicatable() to MachineInstr::isPredicable().

llvm-svn: 37115

not being generated correctly because the shl operator does not mutate its
object but returns a new value. Also, make the distinction between radix
16 and the others more clear.

llvm-svn: 37111

llvm-svn: 37109

llvm-svn: 37108

llvm-svn: 37107

llvm-svn: 37106

llvm-svn: 37105

runtime.

llvm-svn: 37104

llvm-svn: 37103

This fixes PR1423

llvm-svn: 37102

llvm-svn: 37101

llvm-svn: 37100

llvm-svn: 37099

llvm-svn: 37098

llvm-svn: 37097